EP0432524A2
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EP
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Cache memory architecture
Assignee: International Business Machines Corp
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Filing: 1990-11-20
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Granted: —
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Expires: 2010-11-20
Abstract
Abstract A pseudo two-port "snoopy" cache architecture is provided with an associative cache memory and a directory. The cache memory incorporates read/modify/write capability wherein read and write operations may be performed within a single memory cycle. The cache controls include a line state array memory having a plurality of state bits for each entry in the cache directory and is provided with addressing means whereby whenever the directory is accessed, a corresponding state pattern will be accessed in the line state array. The cache-memory also includes with a reload buffer for writing data into the cache and a store back buffer for writing data from the cache into the main memory. The controls for the cache directory execute two complete directory cycles within the time it takes to execute a single cache memory access. "Snooping" operations are performed against the system during alternate directory cycles and CPU access operations are performed during intervening cycles. The cache memory controls effect read/write operations in said cache contingent upon the current state of "state bits" in an accessed line of the line state array memory and selectively modify the state bits if necessary. The memory controls prevent data in the store back buffer from ever becoming dirty by loading said store back buffer in a single cache memory cycle immediately thereafter obtaining control of said memory bus and storing said data back to main memory before any other "bus master" can obtain control of said bus. The controls further include procedures for accessing a "dirty" bit in the state array at an address of a to-be-replaced line in the cache when the reload buffer is full and ready to write data into the cache. The dirty bit indicates if a store-back operation is necessary.
Inventors
- 👤 Chiao-Mei Chuang
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 17:04
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F12/0804; G06F12/0844; G06F12/0855; G06F12/0859
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
175 words
Cache memory, of a hierarchical memory system, where that cache memory is connected to a main memory by a memory bus and to a CPU selectively by a system bus or cache bus, characterized by three associative memory elements each accessible by a common addressing means, a cache memory (40), a cache directory (10), and a line state array (16), memory control means for operating said cache memory system including means for periodically snooping the memory bus at least once for every cache memory cycle, buffer means associated with the cache memory for temporarily storing data to be stored in the cache memory and for temporarily storing data to be transferred from the cache memory to main memory, said cache memory including means for performing read-modify-write operations in a single memory cycle, said memory control means being operable to cause data to be read from said cache memory into said buffer means and written from said buffer means into said cache memory within a single single read-modify-write memory cycle whereby pseudo two-port operation is effected.
Claim 2
Dependent Claim
43 words
Cache memory as set forth in claim 1, characterized in that the buffer means comprises a separate store back buffer (46) for transferring data from said cache memory to main memory and a reload buffer (42) for writing data into said cache memory.
Claim 3
Dependent Claim
87 words
Cache memory system as set forth in claim 2, characterized in that the memory control means includes means operable when a store back of data from the cache to main memory is required, to retain the data line in the cache memory until control of the memory bus is obtained by the cache and then transferring the data from the cache memory to the store back buffer and hence to the memory bus before any other instrumentality connected to the memory bus can gain control of same.
Claim 4
Dependent Claim
94 words
Cache memory system as set forth in claim 3, characterized in that the memory control means includes means for operating the directory at twice the speed of the cache memory and means to cause the directory to alternately snoop the memory bus and serve CPU access requests on consecutive cycles, means operative in response to a snoop hit to cause the contents of a plurality of state bits in the line state array at an address corresponding to the address of the snoop hit to be altered to reflect the circumstances causing the hit.
Claim 5
Dependent Claim
53 words
Cache memory system as set forth in claim 4, characterized in that the control means includes for snooping the address of the data in the reload buffer concurrently with the addresses stored in the said directory for a possible hit and for preventing data stored in the reload buffer from ever becoming dirty.
Claim 6
Dependent Claim
120 words
Cache memory subsystem for use in a large hierarchical memory organization characterized by a cache memory for storing data accessed from an attached main memory and CPU and a cache directory for storing the complete addresses of data stored at related locations in said cache memory, control means for operating said directory at twice the cycle speed of said cache memory, control means for snooping all memory requests in the overall memory system organization against the contents of the directory and serving CPU access requests on alternate directory cycles, and input and output buffering means associated with the cache memory means for controlling the cache memory to provide read-modify-write capabilities within a single memory cycle to achieve pseudo two-port operation.
Claim 7
Dependent Claim
49 words
Cache memory subsystem as set forth in claim 6, characterized in that the cache memory utilizes a read-modify-write cache cycle whereby first data may be read from said cache and second data may be written into said cache during a single memory cycle from and to different buffer registers.
Claim 8
Dependent Claim
107 words
Cache memory subsystem as set forth in claim 7, characterized in that the means for reading and writing data into said cache memory comprises a separate reload buffer for temporarily storing data to be loaded into said cache from the main memory and a separate store back buffer for temporarily storing data read from said cache to be stored back into the main memory, the control means including means operable to prevent data stored in said store back buffer from being modified in memory by any other instrumentality connected to said memory bus before said data is transferred from said store back buffer into said main memory.
Claim 9
Dependent Claim
67 words
Cache memory subsystem as set forth in claim 8, characterized by means for temporarily storing the address in main memory of the data stored in the reload buffer, and means for snooping this address together with all addresses in said cache directory during a snooping operation, and means for preventing any data in the reload buffer from becoming dirty before it is transferred to the cache memory.
Claim 10
Dependent Claim
91 words
Cache memory subsystem as set forth in claim 9, characterized in that the memory subsystem further includes a state machine array having a plurality of bit positions settable by said system controls corresponding to every data line and address in said cache directory and cache memory and concurrently accessible therewith whenever a line in the directory or array is accessed, and means for setting said state array bits to reflect the instantaneous condition of corresponding data in said cache memory in accordance with the utilization of said data by the system.
Claim 11
Dependent Claim
199 words
Pseudo two-port "snoopy" cache architecture, characterized by an associative cache memory and associated directory, said cache memory including a read/modify/write capability wherein read and write operations may be performed within a single memory cycle, controls means for said cache memory including a line state array memory having a plurality of state bits for each entry in the cache memory and directory and common addressing means for said cache memory, directory and line state array operative, whenever the directory is accessed, to access a corresponding state pattern from the line state array, said control memory being operable to execute two complete cache directory cycles for every single cache memory cycle, means for performing "Snooping" operations against the system buses during alternate directory cycles and CPU access operations are during intervening cycles. said controls including means for performing read/write operations in said cache contingent upon the setting of corresponding "state bits" in an accessed line of the line state array memory and for selectively modifying the state bits when required, and means for transferring data from the cache memory into the store back buffer and from the reload buffer into the cache at the same location within a single read-modify-write cycle.
Claim 12
Dependent Claim
118 words
Pseudo two-port 'snoopy' cache architecture as set forth in claim 11, characterized by memory controls for preventing data in the store back buffer from ever becoming dirty by leading said store back buffer in a single cache memory cycle and immediately thereafter obtaining control of said memory bus and storing said data back to main memory before any other "bus master" can obtain control of said bus and means operable for accessing a "dirty" bit in the state array at an address of a to-be-replaced line in the cache when the ready to write data into the cache and means operatable in response thereto for requesting a store back operation if the line is found to be dirty.
References Cited (Backward Citations)
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