Priority control apparatus for a bus in a bus control system having input/output devices

Claim 2

A bus control system comprising: a. bus means for transferring data and a control command therethrough; b. memory means connected to said bus means for storing data transferred through said bus means; c. first data processing means connected to said bus means for processing data and exchanging data with at least said memory means through said bus means; d. second processing means connected to said bus means for processing data transferred through said bus means at a higher speed than said first processing means and exchanging data with at least said memory means through said bus means, said second processing means functioning in the role of processing of data by the first processing means; e. input/output means connected to said bus means for exchanging data with at least said memory means and for processing input/output data; f. bus control means for checking if bus requests for the use of said bus means are issued from said first processing means, said second processing means and said input/output means and for issuing a bus acknowledgment for the use of said bus means to one of said first processing means, said second processing means and said input/output means whose bus request is accepted; g. priority resolution means for setting priorities for the acknowledgment to the requests for the use of said bus means from said first processing means, said second processing means and said input/output means in the order of said input/output means, said second processing means and said first processing means; h. inhibit signal generating means for continuously generating an inhibit signal to be used to inhibit the use of said bus means by said first data processing means when said second processing means continuously uses said bus means; i. said bus control means including means associated with each input/output device, the second processing means and the first data processing means for generating a bus acknowledgment in response to a received bus request if a higher priority bus request has not been received, and gate means coupled to the inhibit signal generating mean which passes the bus acknowledgment of the first processor when the inhibit signal is not present and when a higher priority bus request is not present and suppresses the generation of the bus acknowledgment signal by the means for generating a bus acknowledgment signal associated with the first processing means when the inhibit signal is present; and j. bus usage inhibit means provided in said bus control means for receiving said inhibit signal and continuously the issuing of a bus acknowledgment by said first data processing means to prevent usage of said bus means by said first data processing means.

Claim 3

A bus control system according to claim 1, further comprising interruption request processing means for detecting any interruption request from said input/output means and for issuing, upon detection of the interruption request, an interruption request to said first processing means and said second processing means.

Claim 4

A bus control system according to claim 1, wherein said system further comprises decode means for decoding said control command as a reinitiation command from said first processing means to reinitiate the processing operation of said second processing means which is in a waiting state consequent from an interruption request issued by said input/output means.

Claim 5

A bus control system according to claim 1, wherein said priority resolution means includes priority resolution means for a plurality of input/output means.

Claim 6

A bus control system according to claim 1, wherein said inhibit signal generating means generates said inhibit signal in a timed relation with the issuance to said bus control means of the bus request for the use of said bus means by said second processing means.

Claim 7

A bus control system according to claim 5, wherein said inhibit signal generating means generates said inhibit signal upon issuance to said bus control means from said second processing means of the bus request for the use of said bus means by said second processing means.

Claim 8

A bus control system according to claim 6, wherein said inhibit signal generating means continuously generates said inhibit signal over a predetermined time period commencing at the issuance of said bus request even after said request terminates.

Claim 9

A bus control system according to claim 1, wherein said inhibit signal generating means continuously generates said inhibit signal over a period in which said second processing means makes access to said memory means a plurality of times through said bus means.

Claim 10

A bus control system according to claim 1, wherein said bus control means allows the use of said bus means by said first data processing means when said bus control means accepts the bus request from said first processing means for the use of said bus means during a period when said inhibit signal generating means does not issue said inhibit signal in the absence of the bus request from said input/output means and said second processing means for the use of said bus means by said input/output means and said second processing means.

Claim 11

A bus control system comprising: a. bus means for transferring data and a control command therethrough; b. memory means connected to said bus means for storing data transferred through said bus means; c. first data processing means connected to said bus means for processing data and exchanging data with at least said memory means through said bus means; d. second processing means connected to said bus means for processing data transferred through said bus means at a higher speed than said first processing means and exchanging data with at least said memory means through said bus means, said second processing means functioning in the role of processing of data by the first processing means; e. input/output means connected to said bus means for exchanging data with at least said memory means and for processing input/output data; f. bus control means for checking if bus requests for the use of said bus means are issued from said first processing means, said second processing means and said input/output means and for issuing a bus acknowledgment for the use of said bus means to one of said first processing means, said second processing means and said input/output means whose bus request is accepted; g. priority resolution means for setting priorites for the acknowledgment to the requests for the use of said bus means from said first processing means, said second processing means and said input/output means in the order of said input/output means, said second processing means and said first processing means; h. inhibit signal generating means for continuously generating an inhibit signal to be used to inhibit the use of said bus means by said first data processing means when said second processing means continuously uses said bus means; i. said bus control means including a means associated with each input/output device, the second processing means and the first data processing means for generating a bus acknowledgment in response to a received bus request if a higher priority bus request has not yet been received, and gate means coupled to the inhibit signal generating means which passes the bus acknowledgment of the first processor when the inhibit signal is not present and when a higher priority bus request is not present and suppresses the generation of the bus acknowledgment signal by the means for generating a bus acknowledgment signal associated with the first processing means when the inhibit signal is present; j. bus usage inhibit means provided in said bus control means for receiving said inhibit signal and continuously inhibiting the issuing of a bus acknowledgment by said first data processing means to prevent usage of said bus means by said first data processing means; k. interruption request processing means for detecting any interruption request from said input/output means and for issuing, upon detection of the interruption request, an interruption request to said first processing means and said second processing means; and l. decode means for decoding said control command as a reinitiation command from said first processing means to reinitiate the processing operation of said second processing means which is in a waiting state consequent from an interruption request issued by said input/output means.

Claim 12

A bus control system comprising: a. bus means for transferring data and a control command therethrough; b. memory means connected to said bus means for storing data transferred through said bus means; c. first data processing means connected to said bus means for processing data and exchanging data with at least said memory means through said bus means; d. second processing means connected to said bus means for processing data transferred through said bus means at a higher speed than said first processing means and exchanging data with at least said memory means through said bus means, said second processing means functioning in the role of processing of data by the first processing means; e. input/output means connected to said bus means for exchanging data with at least said memory means and for processing input/output data; f. bus control means for checking if bus requests for the use of said bus means are issued from said first processing means, said second processing means and said input/output means and for issuing a bus acknowledgment for the use of said bus means to one of said first processing means, said second processing means and said input/output means whose bus request is accepted; g. priority resolution means for setting priorites for the acknowledgment to the requests for the use of said bus means from said first processing means, said second processing means and said input/output means in the order of said input/output means, said second processing means and said first processing means; h. inhibit signal generating means for continuously generating an inhibit signal to be used to inhibit the use of said bus means by said first data processing means when said second processing means continuously uses said bus means; i. said bus control means including a means associated with each input/output device, the second processing means and the first data processing means for generating a bus acknowledgment in response to a received bus request if a higher priority bus request has not yet been received, and gate means coupled to the inhibit signal generating means which passes the bus acknowledgment of the first processor when the inhibit signal is not present and when a higher priority bus request is not present and suppresses the generation of the bus acknowledgment signal by the means for generating a bus acknowledgment signal associated with the first processing means when the inhibit signal is present; j. bus usage inhibit means provided in said bus control means for receiving said inhibit signal and continuously inhibiting the issuing of a bus acknowledgment by said first data processing means to prevent usage of said bus means by said first data processing means; k. interruption request processing means for detecting any interruption request from said input/output means and for issuing, upon detection of the interruption request, an interruption request to said first processing means and said second processing means; and l. decode means for decoding said control command as a reinitiation command from said first processing means to reinitiate the processing operation of said second processing means which is in a waiting state consequent from an interruption request issued by said input/output means.

Claim 13

A bus control system according to claim 10, wherein said priority resolution means includes priority resolution means for a plurality of input/output means.

Claim 14

A bus control system acccording to claim 10, wherein said inhibit signal generating means generates said inhibit signal in a timed relation with the issuance to said bus control means of the bus request for the use of said bus means by said second processing means.

Claim 15

A bus control system according to claim 12, wherein said inhibit signal generating means generates said inhibit signal upon issuance to said bus control means from said second processsing means of the bus request for the use of said bus means by said second processing means.

Claim 16

A bus control system according to claim 13, wherein said inhibit signal generating means continuously generates said inhibit signal over a predetermined time period commencing at the issuance of said bus request even after said request terminates.

Claim 17

A bus control system according to claim 10, wherein said inhibit signal generating means continuously generates said inhibit signal over a period in which said second processing means makes access to said memory means a plurality of times through said bus means.

Claim 18

A bus control system according to claim 10, wherein said bus control means allows the use of said bus means by said first data processing means when said bus control means accepts the bus request from said first processing means for the use of said bus means during a period when said inhibit signal generating means does not issue said inhibit signal in the absence of the bus request from said input/output means and said second processing means for the use of said bus means by said input/output means and said second processing means.