Memory cell array having compact word line arrangement

Claim 2

A semiconductor memory array, comprising: two memory blocks, each having a plurality of rows of memory cells; a word line that extends into said two memory blocks; a word line driver for providing drive signals to said word line; two pairs of subword lines each subword line of each pair being associated with memory cells of a respective one of said plurality of rows of memory cells in a respective one of said blocks; two pairs of subword line drivers, each pair connected to opposite ends of said word line within a respective one of said two blocks, each subword line driver selectively delivering drive signals from said word line to a respective one of said subword lines; and a plurality of selection signal lines, each selection signal line connected to select a respective one of said subword line drivers to control delivery of drive signals from said word line to said respective one of said subword lines.

Claim 3

The semiconductor memory array of claim 1 wherein said drive signals include read select and deselect signals, erase select and deselect signals, and program select and deselect signals.

Claim 4

The semiconductor memory array of claim 1 wherein said subword lines are located on opposite sides of said word line.

Claim 5

The semiconductor memory array of claim 1 wherein said selection signal lines are oriented orthogonally to said word line at opposite ends of said word line within a respective one of said two blocks.

Claim 6

The semiconductor memory array of claim 1 wherein said word line is metal.

Claim 7

The semiconductor memory array of claim 1 wherein said subword lines are polysilicon.

Claim 8

The semiconductor memory array of claim 1 further comprising two additional pair of subword lines, each subword line of each additional pair being associated with memory cells of a respective additional one of said plurality of rows of memory cells in a respective one of said blocks, two additional pair of subword line drivers, each additional pair connected to opposite ends of said word line within a respective one of said two blocks, each additional subword line driver selectively delivering drive signals from said word line to a respective one of said additional subword lines, and an additional plurality of selection signal lines, each additional selection signal line connected to select a respective one of said additional subword line drivers to deliver drive signals from said word line to said respective additional one of said subword lines.

Claim 9

The semiconductor memory array of claim 7 wherein each subword line of each additional subword line pair, and each subword line driver of each additional subword line driver pair are located on opposite sides of said word line.

Claim 10

A semiconductor memory array, comprising: a plurality of memory blocks, each having a plurality of rows of memory cells; a plurality of word lines, each extending across at least two of said plurality of memory blocks; a plurality of word line drivers, each for providing drive signals to a respective one said word lines; a plurality of subword line pairs, each pair associated with a respective one of said word lines within a respective one of said memory blocks, each subword line being associated with memory cells of a respective one of said plurality of rows of memory cells in said respective one of said blocks; a plurality of pairs of subword line drivers, each pair connected to opposite ends of one of said plurality of word lines within a respective one of said plurality of blocks, each subword line driver selectively delivering drive signals from said word line to a respective one of said subword lines; and a plurality of selection signal lines, each selection signal line connected to a respective one of said subword line drivers to control delivery of drive signals from said word line to said respective one of said subword lines.

Claim 11

A semiconductor memory array, comprising: a plurality of memory blocks, each having a plurality of rows of memory cells; a plurality of word lines, each extending across at least two of said plurality of memory blocks; a plurality of word line drivers, each for providing drive signals to a respective one said word lines; a plurality of subword line pairs, each pair associated with a respective one of said word lines within a respective one of said memory blocks, each subword line being associated with memory cells of a respective one of said plurality of rows of memory cells in said respective one of said blocks; a plurality of pairs of subword line drivers, each pair connected to opposite ends of one of said plurality of word lines within a respective one of said plurality of blocks, each subword line driver selectively delivering drive signals from said word line to a respective one of said subword lines; and a plurality of selection signal lines, each selection signal line connected to a respective one of said subword line drivers to control delivery of drive signals from said word line to said respective one of said subword lines.

Claim 12

The semiconductor memory array of claim 9 wherein said drive signals include read select and deselect signals, erase select and deselect signals, and program select and deselect signals.

Claim 13

The semiconductor memory array of claim 9 wherein each of said selection signal lines connects to every other subword line driver within each block.

Claim 14

The semiconductor memory array of claim 9 wherein said subword lines of each pair of subword lines are located on opposite sides of a portion of said word line within a respective one of said memory blocks.

Claim 15

The semiconductor memory array of claim 9 wherein said selection signal lines are oriented orthogonally to said word lines at opposite ends of said word line within respective ones of said memory blocks.

Claim 16

The semiconductor memory array of claim 9 wherein said word lines are metal.

Claim 17

The semiconductor memory array of claim 9 wherein said subword lines are polysilicon.

Claim 18

The semiconductor memory array of claim 9 further comprising two additional pair of subword lines, each subword line of each additional pair being associated with memory cells of a respective additional one of said plurality of rows of memory cells in a respective one of said memory blocks, two additional pair of subword line drivers, each additional pair of subword line drivers connected to opposite ends of said word line within a respective one of said memory blocks, each additional subword line driver selectively delivering drive signals from said word line to a respective one of said additional subword lines, and an additional plurality of selection signal lines, each additional selection signal line connected to select a respective one of said additional subword line drivers to deliver drive signals from said word line to said respective additional one of said subword lines.

Claim 19

The semiconductor memory array of claim 16 wherein each subword line of each additional subword line pair, and each subword line driver of each additional subword line driver pair are located on opposite sides of a portion of said word line within a respective one of said memory blocks.

Claim 22

The method of claim 18 wherein said drive signals include read select and deselect signals, erase select and deselect signals, and program select and deselect signals.

Claim 23

The method of claim 18 wherein said step of arranging two pairs of subword lines comprises arranging said subword lines of each pair on opposite sides of a respective portion of said word line within one of said two memory blocks.

Claim 24

The method of claim 18 wherein said step of arranging two pairs of subword lines comprising arranging said subword lines of each pair on a same side of a respective portion of said word line within one of said two memory blocks.

Claim 25

The method of claim 18 wherein said step of connecting a plurality of selection signals lines comprises orienting said selection signal lines orthogonally to said word line at opposite ends of said word line within respective ones of said two memory blocks.

Claim 26

A subword line driver circuit for use in a semiconductor memory array having at least two blocks of memory cells, a word line, a subword line, first and second block select lines, and a common source line, comprising: a first NMOS transistor having a gate, a drain, and a source; a first PMOS transistor having a gate, a drain, and a source; the drain of the first NMOS transistor and the source of the first PMOS transistors being connected to the word line, the source of the first NMOS transistor and drain of the first PMOS transistor being connected to receive a signal from the common source line, the gate of the first NMOS transistor being connected to the first block select line, and the gate of the first PMOS transistor being connected to the second block select line.

Claim 27

A subword line driver circuit for use in a semiconductor memory array having at least two blocks of memory cells, a word line, a subword line, first and second block select lines, and a common source line, comprising: a first NMOS transistor having a gate, a drain, and a source; a first PMOS transistor having a gate, a drain, and a source; the drain of the first NMOS transistor and the source of the first PMOS transistors being connected to the word line, the source of the first NMOS transistor and drain of the first PMOS transistor being connected to receive a signal from the common source line, the gate of the first NMOS transistor being connected to the first block select line, and the gate of the first PMOS transistor being connected to the second block select line.

Claim 28

The subword line driver circuit of claim 23 wherein said first block select line is a true block select line and said second block select line is a complement block select line.

Claim 29

The subword line driver circuit of claim 23 wherein said first block select line is a complement block select line and said second block select line is a true block select line.

Claim 30

The subword line driver circuit of claim 23 further comprising: a second NMOS transistor having a gate, a drain, and a source; a second PMOS transistor having a gate, a drain, and a source; the drain of the second NMOS transistor and the source of the second PMOS transistor being connected to the drain respectively of the first PMOS transistor and the source of the first NMOS transistor, the source of the second NMOS transistor and the drain of the second PMOS transistors being connected to receive a signal on the common source line, the gate of the second NMOS transistor being connected to the second block select line, and the gate of the second PMOS transistor being connected to the first block select line.

Claim 31

The subword line driver circuit of claim 23 wherein the memory cells are constructed in a well of p-type conductivity in a semiconductor substrate and further comprising separate connections to the well and to the channel of the NMOS transistor.

Claim 32

The subword line driver circuit of claim 23 wherein the memory cells are constructed in a well of n-type conductivity in a semiconductor substrate and further comprising separate connections to the well and to the channel of the PMOS transistor.

Claim 33

A subword line driver circuit for use in a semiconductor memory array having at least two blocks of memory cells, a word line, a subword line, a block select line, a block complement select line, and a common source line, comprising: first and second NMOS transistors, each having a gate, a drain, and a source; first and second PMOS transistors, each having a gate, a drain, and a source; the drain of the first NMOS transistor and the source of the first PMOS transistor being connected to the word line, the source of the first NMOS transistor and the drain of the first PMOS transistor being connected to the respective source of the second PMOS transistor and the drain of the second NMOS transistor, the gates of the first NMOS transistor and second PMOS transistor being connected to the block select line, and the gates of the second NMOS transistor and first PMOS transistor being connected to the block complement select line.

Claim 34

A subword line driver circuit for use in a semiconductor memory array having at least two blocks of memory cells, a word line, a subword line, a block select line, a block complement select line, and a common source line, comprising: first and second NMOS transistors, each having a gate, a drain, and a source; first and second PMOS transistors, each having a gate, a drain, and a source; the drain of the first NMOS transistor and the source of the first PMOS transistor being connected to the word line, the source of the first NMOS transistor and the drain of the first PMOS transistor being connected to the respective source of the second PMOS transistor and the drain of the second NMOS transistor, the gates of the first NMOS transistor and second PMOS transistor being connected to the block select line, and the gates of the second NMOS transistor and first PMOS transistor being connected to the block complement select line.

Claim 35

The subword line driver circuit of claim 29 wherein the memory cells are constructed in a well of p-type conductivity in a semiconductor substrate and further comprising separate connections to the well and to the channels of the first and second NMOS transistors.

Claim 36

The subword line driver circuit of claim 29 wherein the memory cells are constructed in a well of n-type conductivity in a semiconductor substrate and further comprising separate connections to the well and to the channels of the first and second PMOS transistors.

Claim 37

A semiconductor memory array, comprising: two memory blocks, each having a plurality of rows of memory cells; a word line that extends into said two memory blocks; a word line driver for providing drive signals to said word line; two pairs of subword lines each subword line of each pair being associated with memory cells of a respective one of said plurality of rows of memory cells in a respective one of said blocks; two pairs of subword line drivers, each pair connected to opposite ends of said word line within a respective one of said two blocks, each subword line driver selectively delivering drive signals from said word line to a respective one of said subword lines; a plurality of selection signal lines, each selection signal line connected to select a respective one of said subword line drivers to control delivery of drive signals from said word line to said respective one of said subword lines; each of said subword drivers comprising: first and second NMOS transistors, each having a gate, a drain, and a source; first and second PMOS transistors, each having a gate, a drain, and a source; the drain of the first NMOS transistor and the source of the first PMOS transistor being connected to the word line, the source of the first NMOS transistor and the drain of the first PMOS transistor being connected to the respective source of the second PMOS transistor and the drain of the second NMOS transistor the source of the first NMOS transistor and the drain of the first PMOS transistor being also connected to one of said subword lines, the drain of said second PMOS transistor and the source of said second NMOS transistor being connected to a common source line, the gates of the first NMOS transistor and second PMOS transistor being connected to one of said block selection lines, and the gates of the second NMOS transistor and first PMOS transistor being connected to a complement selection line.

Claim 38

A semiconductor memory array, comprising: two memory blocks, each having a plurality of rows of memory cells; a word line that extends into said two memory blocks; a word line driver for providing drive signals to said word line; two pairs of subword lines each subword line of each pair being associated with memory cells of a respective one of said plurality of rows of memory cells in a respective one of said blocks; two pairs of subword line drivers, each pair connected to opposite ends of said word line within a respective one of said two blocks, each subword line driver selectively delivering drive signals from said word line to a respective one of said subword lines; a plurality of selection signal lines, each selection signal line connected to select a respective one of said subword line drivers to control delivery of drive signals from said word line to said respective one of said subword lines; each of said subword drivers comprising: first and second NMOS transistors, each having a gate, a drain, and a source; first and second PMOS transistors, each having a gate, a drain, and a source; the drain of the first NMOS transistor and the source of the first PMOS transistor being connected to the word line, the source of the first NMOS transistor and the drain of the first PMOS transistor being connected to the respective source of the second PMOS transistor and the drain of the second NMOS transistor the source of the first NMOS transistor and the drain of the first PMOS transistor being also connected to one of said subword lines, the drain of said second PMOS transistor and the source of said second NMOS transistor being connected to a common source line, the gates of the first NMOS transistor and second PMOS transistor being connected to one of said block selection lines, and the gates of the second NMOS transistor and first PMOS transistor being connected to a complement selection line.

Claim 39

The semiconductor memory array of claim 32 wherein said drive signals include read select and deselect signals, erase select and deselect signals, and program select and deselect signals.

Claim 40

The semiconductor memory array of claim 32 wherein said subword lines are located on opposite sides of said word line.

Claim 41

The semiconductor memory array of claim 32 wherein said selection signal lines are oriented orthogonally to said word line at opposite ends of said word line within respective ones of said two blocks.

Claim 42

The semiconductor memory array of claim 32 wherein said word line is metal.

Claim 43

The semiconductor memory array of claim 32 wherein said subword lines are polysilicon.

Claim 44

A word line driver circuit for use in a semiconductor memory array having at least two blocks of memory cells, comprising: a first word line for supplying signals for delivery to a selected memory cell; a source line for supplying signals for delivery to a deselected memory cell; a first block select line for carrying true block select signals; a second block select line for carrying complement block select signals; a second word line for delivering signals selected from said first word line and said source line to a plurality of memory cells in said at least two blocks; first and second NMOS transistors, each having a gate, a drain, and a source; first and second PMOS transistors, each having a gate, a drain, and a source; the drain of the first NMOS and source of the first PMOS transistors being connected to the first word line, the source of the first NMOS and drain of the first PMOS transistors being connected to the second word line and to the drain respectively of the second NMOS and source of the second PMOS transistors; the gates of the first NMOS transistor and the second PMOS transistor being connected to the first block select line, and the gates of the first PMOS transistor and the second NMOS transistor being connected to the second block select line, and the source of the second NMOS and drain of the second PMOS transistors being connected to the source line, whereby said second word line delivers signals selected from said first word line and said source line to said memory cells in dependence upon the true and complement block select signals on said first and second block select lines.

Claim 45

A word line driver circuit for use in a semiconductor memory array having at least two blocks of memory cells, comprising: a first word line for supplying signals for delivery to a selected memory cell; a source line for supplying signals for delivery to a deselected memory cell; a first block select line for carrying true block select signals; a second block select line for carrying complement block select signals; a second word line for delivering signals selected from said first word line and said source line to a plurality of memory cells in said at least two blocks; first and second NMOS transistors, each having a gate, a drain, and a source; first and second PMOS transistors, each having a gate, a drain, and a source; the drain of the first NMOS and source of the first PMOS transistors being connected to the first word line, the source of the first NMOS and drain of the first PMOS transistors being connected to the second word line and to the drain respectively of the second NMOS and source of the second PMOS transistors; the gates of the first NMOS transistor and the second PMOS transistor being connected to the first block select line, and the gates of the first PMOS transistor and the second NMOS transistor being connected to the second block select line, and the source of the second NMOS and drain of the second PMOS transistors being connected to the source line, whereby said second word line delivers signals selected from said first word line and said source line to said memory cells in dependence upon the true and complement block select signals on said first and second block select lines.

Claim 46

The word line driver circuit of claim 38 wherein the memory cells are constructed in a well of p-type conductivity in a semiconductor substrate and further comprising separate connections to the well and to the channels of the NMOS transistors.

Claim 47

The word line driver circuit of claim 38 wherein the memory cells are constructed in a well of n-type conductivity in a semiconductor substrate and further comprising separate connections to the well and to the channels of the PMOS transistors.

Claim 48

The word line driver circuit of claim 38 wherein the first word line is a main word line, and the second word line is a subword line.

Claim 49

The word line driver circuit of claim 38 wherein the first word line is an enable signal line, and the second word line is a main word line.