US5018108A
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Nonvolatile semiconductor memory
Assignee: Toshiba Corp
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Filing: 1989-06-06
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Granted: 1991-05-21
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Expires: 2009-06-06
Abstract
Abstract A memory cell array includes a matrix array of a plurality of memory cells. These memory cells are non-volatile transistors. The memory cells which are arrayed in each row of the memory array, are coupled with a plurality of word lines. The word lines are selected by a row decoder made up of a plurality of partial decoders. In this case, a constant voltage output circuit, which is provided at the outputs of the partial decoders of the row decoder, outputs a constant voltage lower than a power source voltage to a corresponding word line of those word lines when the corresponding word line is selected by the outputs of the partial decoders.
Inventors
- 👤 Tadashi Maruyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:31
CPC Classifications
G; G11; G11C; G11C17/00; G11C16/00; G11C16/02; G11C16/06; G11C16/08
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
241 words
A nonvolatile semiconductor memory comprising: a memory cell array in which a plurality of memory cells are arrayed in rows and columns in a matrix fashion, each said memory cell including a nonvolatile transistor having a source, gate, and drain, said nonvolatile transistor storing data as a high level or as a low level; a plurality of word lines coupled with the gates of said nonvolatile transistors, said plurality of memory cells being arrayed in the rows of said memory array; a row decoder including a plurality of partial decoders for selecting one of said plurality of word lines; a constant voltage output circuit for receiving the outputs of said partial decoders of said row decoder, and for outputting a constant voltage to said selected one of said plurality of word lines, said constant voltage being a potential substantially halfway between a first and a second threshold voltage that respectively correspond to the high and low levels of the stored data and being used as a voltage for reading the stored data; a plurality of bit lines coupled with the drains of said nonvolatile transistors, said plurality of memory cells being arrayed in the columns of said memory array; a column decoder including a plurality of partial decoders for selecting one of said plurality of bit lines; and a sense amplifier to be coupled with one of said plurality of bit lines selected by an output signal of said column decoder.
Claim 2
Dependent Claim
241 words
A nonvolatile semiconductor memory comprising: a memory cell array in which a plurality of memory cells are arrayed in rows and columns in a matrix fashion, each said memory cell including a nonvolatile transistor having a source, gate, and drain, said nonvolatile transistor storing data as a high level or as a low level; a plurality of word lines coupled with the gates of said nonvolatile transistors, said plurality of memory cells being arrayed in the rows of said memory array; a row decoder including a plurality of partial decoders for selecting one of said plurality of word lines; a constant voltage output circuit for receiving the outputs of said partial decoders of said row decoder, and for outputting a constant voltage to said selected one of said plurality of word lines, said constant voltage being a potential substantially halfway between a first and a second threshold voltage that respectively correspond to the high and low levels of the stored data and being used as a voltage for reading the stored data; a plurality of bit lines coupled with the drains of said nonvolatile transistors, said plurality of memory cells being arrayed in the columns of said memory array; a column decoder including a plurality of partial decoders for selecting one of said plurality of bit lines; and a sense amplifier to be coupled with one of said plurality of bit lines selected by an output signal of said column decoder.
Claim 3
Dependent Claim
65 words
The nonvolatile semiconductor memory according to claim 1, wherein said constant voltage output circuit includes a plurality of MOS transistors, each said MOS transistor is of the depletion type whose source-drain path is inserted in series between an output terminal of the corresponding partial decoder in said row decoder and the corresponding word line, and whose gate is coupled with a second power source voltage.
Claim 4
Dependent Claim
18 words
The nonvolatile semiconductor memory according to claim 2, wherein said second power source voltage is a ground voltage.
Claim 5
Dependent Claim
60 words
The nonvolatile semiconductor memory according to claim 2, wherein a threshold voltage of each said MOS transistor is set substantially at a mid potential between a threshold voltage of a nonelectron injected memory cell and that of an electron injected memory cell in an initial stage of said semiconductor memory immediately after data is programmed into each said memory cell.
Claim 6
Dependent Claim
123 words
The nonvolatile semiconductor memory according to claim 1, wherein said constant voltage output circuit includes: a plurality of first MOS transistors, each said first MOS transistor being of the depletion type whose source-drain path is connected at one end to an output terminal of the corresponding partial decoder in said row decoder, and whose gate is coupled with a second power source voltage; and a plurality of second MOS transistors, each said second MOS transistor being of the depletion type whose source-drain path is inserted in series between the output terminal of the corresponding partial decoder in said row decoder and the corresponding word line, and whose gate is coupled with other end of the source-drain path of a corresponding first MOS transistor.
Claim 7
Dependent Claim
18 words
The nonvolatile semiconductor memory according to claim 5, wherein said second power source voltage is a ground voltage.
Claim 8
Dependent Claim
60 words
The nonvolatile semiconductor memory according to claim 5, wherein a threshold voltage of each said MOS transistor is set substantially at a mid potential between a threshold voltage of a nonelectron injected memory cell and that of an electron injected memory cell in an initial stage of said semiconductor memory immediately after data is programmed into each said memory cell.
Claim 9
Dependent Claim
16 words
The nonvolatile semiconductor memory according to claim 1 wherein said nonvolatile semiconductor memory is an EPROM.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-05-20 | 1994-11-19 | 1995-05-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-20 | 1998-11-19 | 1999-05-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-20 | 2002-11-19 | 2003-05-21 | $7700.00 | Window Closed / Lapsed |