Semiconductor memory device of divided word line

Claim 2

A semiconductor memory device having a decoder responsive to a first select signal for row selection and a second select signal for block selection to activate or deactivate a predetermined select signal, said decoder comprising: first, second, third and fourth lines carrying, respectively, the first select signal, the second select signal, the predetermined select signal and a ground potential; a first field effect transistor of p-type polarity having source, drain and gate electrodes; a second field effect transistor of n-type polarity having source, drain and gate electrodes; the gates being connected to each other and to the second line for receiving said second select line; the source of said second field effect transistor being connected to the fourth line for receiving the ground potential, said second field effect transistor being rendered conductive when said first select signal is inactivated; the source of said first field effect transistor connected to said first line for receiving said first select signal, said first field effect transistor being rendered conductive when said first select signal is activated for applying said second select signal to said third line; the drains of said first and second field effect transistors being connected to each other and to said third line for supplying said predetermined select signal; and forcing means for forcing the potential on said third select line to a potential corresponding to an inactivated state when at least one of said first select signal on said first signal line and said second select signal on said second signal line is inactivated.

Claim 3

The semiconductor memory device according to claim 1, wherein said forcing means includes third switching means of n-type polarity being rendered conductive when said first select signal is activated, for applying said second select signal to said predetermined select signal.

Claim 4

The semiconductor memory device according to claim 1, wherein said forcing means includes third switching means of n-type polarity being rendered conductive when said second select signal is inactivated, for applying said second select signal to said predetermined select signal.

Claim 5

The semiconductor memory device according to claim 1, wherein said forcing means includes resistance means coupled between said third signal line and said fourth signal line.

Claim 6

The semiconductor memory device according to claim 4, wherein said resistance means includes a resistance element having a large resistance value.

Claim 7

The semiconductor memory device according to claim 4, wherein said resistance means includes transistor means having a large on-resistance value.

Claim 8

The semiconductor memory device according to claim 2 wherein said first select signal includes first and second signals complementary to each other.

Claim 9

The semiconductor memory device according to claim 3, wherein said second select signal includes first and second signals complementary to each other.

Claim 10

A semiconductor memory device comprising a decoder responsive to first and second select signals for operating to activate or inactivate a predetermined select line; said decoder including first and second decoder circuit means, said predetermined select line including first and second select lines, and said first select signal including first and second sub-select signals, said first decoder circuit means including: first switching means being rendered conductive when said first sub-select signal is activated, for applying said second select signal to said first select line, and second switching means coupled between said first select line and a potential corresponding to said inactivated state and being rendered conductive when said first sub-select signal is inactivated, said second decoder circuit means including: third switching means being rendered conductive when said second sub-select signal is activated, for applying said second select signal to said second select line, and fourth switching means coupled between said second select line and said potential corresponding to an inactivated state and being rendered conductive when said second sub-select signal is inactivated.

Claim 11

A semiconductor memory device comprising a decoder responsive to first and second select signals for operating to activate or inactivate a predetermined select line; said decoder including first and second decoder circuit means, said predetermined select line including first and second select lines, and said first select signal including first and second sub-select signals, said first decoder circuit means including: first switching means being rendered conductive when said first sub-select signal is activated, for applying said second select signal to said first select line, and second switching means coupled between said first select line and a potential corresponding to said inactivated state and being rendered conductive when said first sub-select signal is inactivated, said second decoder circuit means including: third switching means being rendered conductive when said second sub-select signal is activated, for applying said second select signal to said second select line, and fourth switching means coupled between said second select line and said potential corresponding to an inactivated state and being rendered conductive when said second sub-select signal is inactivated.

Claim 12

The semiconductor memory device according to claim 9 further comprising forcing means for forcing the potential on said first select line to said potential corresponding to an inactivated state when at least one of said first sub-select signal and said second select signal is inactivated and for forcing the potential on said second select line to said potential corresponding to an inactivated state when at least one of said second sub-select signal and said second select signal is inactivated.

Claim 13

The semiconductor memory device according to claim 10, wherein said forcing means includes: fifth switching means being rendered conductive when said first sub-select signal is activated, for applying said second select signal to said first select line, and sixth switching means being rendered conductive when said second sub-select signal is activated, for applying said second select signal to said second select line.

Claim 14

The semiconductor memory device according to claim 10, wherein said forcing means includes first resistance means coupled between said first select line and said potential corresponding to an inactivated state, and second resistance means coupled between said second select line and said potential corresponding to an inactivated state.

Claim 15

The semiconductor memory device according to claim 10, wherein said forcing means includes signal generating means for generating a signal for once simultaneously rendering said second and fourth switching means conductive prior to said operation of said decoder.

Claim 16

The semiconductor memory device according to claim 11, wherein said first sub-select signal includes first and second signals complementary to each other, and said second sub-select signal includes third and fourth signals complementary to each other.

Claim 17

The semiconductor memory device according to claim 14, wherein said first switching means includes first conductivity type first transistor means being responsive to said first signal, said second switching means includes second conductivity type second transistor means being responsive to said first signal, said third switching means includes third transistor means of said first conductivity type being responsive to said third signal, said fourth switching means includes fourth transistor means of said second conductivity type being responsive to said third signal, said fifth switching means includes fifth transistor means of said second conductivity type being responsive to said second signal, and said sixth switching means includes sixth transistor means of said second conductivity type being responsive to said fourth signal.

Claim 18

The semiconductor memory device according to claim 14, wherein said first switching means includes first transistor means being responsive to said second signal, said second switching means includes second transistor means having the same conductivity type as that of said first transistor means and being responsive to said first signal, said third switching means includes third transistor means being responsive to said fourth signal, said fourth switching means includes fourth transistor means having the same conductivity type as that of said third transistor means and being responsive to said third signal, said fifth switching means includes fifth transistor means having the same conductivity type as those of said first and second transistor means and being responsive to said second signal, and said sixth switching means includes sixth transistor means having the same conductivity type as those of said first and second transistor means and being responsive to said fourth signal.

Claim 19

The semiconductor memory device according to claim 14, wherein said first switching means includes first conductivity type first transistor means being responsive to said first signal, said second switching means includes second transistor means of said first conductivity type being responsive to said second signal, said third switching means includes third transistor means of said first conductivity type being responsive to said third signal, said fourth switching means includes fourth transistor means of said first conductivity type being responsive to said fourth signal, said fifth switching means includes fifth transistor means of a second conductivity type being responsive to said second signal, and said sixth switching means includes sixth transistor means of said second conductivity type being responsive to said fourth signal.

Claim 20

The semiconductor memory device according to claim 12, wherein said first switching means includes first conductivity type first transistor means being responsive to said first sub-select signal, said second switching means includes second conductivity type second transistor means being responsive to said first sub-select signal, said third switching means includes third transistor means of said first conductivity type being responsive to said second sub-select signal, and said fourth switching means includes fourth transistor means of said second conductivity type responsive to said second sub-select signal.

Claim 21

The semiconductor memory device according to claim 12, wherein said first sub-select signal includes first and second signals complementary to each other, said first switching means includes first transistor means being responsive to said first signal, said second switching means includes second transistor means having the same conductivity type as that of said first transistor means and being responsive to said second signal, said second sub-select signal includes third and fourth signals complementary to each other, said third switching means includes third transistor means being responsive to said third signal, and said fourth switching means includes fourth transistor means having the same conductivity type as that of said third transistor means and being responsive to said fourth signal.

Claim 22

The semiconductor memory device according to claim 13, wherein said first switching means includes first conductivity type first transistor means being responsive to said first sub-select signal, said second switching means includes second conductivity type second transistor means being responsive to said first sub-select signal, said third switching means includes third transistor means of said first conductivity type being responsive to said second sub-select signal, and said fourth switching means includes fourth transistor means of said second conductivity type responsive to said second sub-select signal.

Claim 23

The semiconductor memory device according to claim 13, wherein said first sub-select signal includes first and second signals complementary to each other, said first switching means includes first transistor means being responsive to said first signal, said second switching means includes second transistor means having the same conductivity type as that of said first transistor means and being responsive to said second signal, said second sub-select signal includes third and fourth signals complementary to each other, said third switching means includes third transistor means being responsive to said third signal, and said fourth switching means includes fourth transistor means having the same conductivity type as that of said third transistor means and being responsive to said fourth signal.

Claim 24

A semiconductor memory device comprising: a plurality of memory cell array blocks each including a plurality of memory cells and a plurality of local word lines arranged in a plurality of rows, comprising: a main word line pair provided in common for said plurality of memory cell array blocks, first selecting means for applying first and second signals complementary to each other to said main word line pair as a first select signal, a plurality of select line groups provided corresponding to said plurality of memory cell array blocks, each of said plurality of select line groups including a plurality of select lines corresponding to said plurality of local word lines in the corresponding memory cell array block, second selecting means for applying a second select signal to one of said plurality of select lines included in one of said plurality of select line groups, and a plurality of decoder groups provided corresponding to said plurality of memory cell array blocks, each of said plurality of decoder groups including a plurality of decoder means corresponding to said plurality of local word lines in the corresponding memory cell array block, each of said plurality of decoder means being responsive to said first select signal applied to said main word line pair and said second select signal applied to the corresponding one of said select lines for operating to activate the corresponding one of said local word lines.

Claim 25

A semiconductor memory device comprising: a plurality of memory cell array blocks each including a plurality of memory cells and a plurality of local word lines arranged in a plurality of rows, comprising: a main word line pair provided in common for said plurality of memory cell array blocks, first selecting means for applying first and second signals complementary to each other to said main word line pair as a first select signal, a plurality of select line groups provided corresponding to said plurality of memory cell array blocks, each of said plurality of select line groups including a plurality of select lines corresponding to said plurality of local word lines in the corresponding memory cell array block, second selecting means for applying a second select signal to one of said plurality of select lines included in one of said plurality of select line groups, and a plurality of decoder groups provided corresponding to said plurality of memory cell array blocks, each of said plurality of decoder groups including a plurality of decoder means corresponding to said plurality of local word lines in the corresponding memory cell array block, each of said plurality of decoder means being responsive to said first select signal applied to said main word line pair and said second select signal applied to the corresponding one of said select lines for operating to activate the corresponding one of said local word lines.

Claim 26

The semiconductor memory device according to claim 22, wherein each of said plurality of decoder means includes: first switching means being rendered conductive when said first select signal is activated for applying the signal on the corresponding one of said select lines to the corresponding one of said local word lines, and second switching means coupled between said corresponding local word line and a potential corresponding to an inactivated state and being rendered conductive when said first select signal is inactivated.

Claim 27

The semiconductor memory device according to claim 23, wherein each of said plurality of decoder means further includes forcing means for forcing the potential on the corresponding one of said local word lines to said potential corresponding to an inactivated state when at least one of said first select signal and said second select signal applied to the corresponding one of said select lines is inactivated.

Claim 28

The semiconductor memory device according to claim 24, wherein each of said forcing means includes third switching means being rendered conductive when said first select signal is activated, for applying the signal on the corresponding one of said select lines to the corresponding one of said local word lines.

Claim 29

The semiconductor memory device according to claim 24, wherein each of said forcing means includes resistance means coupled between the corresponding one of said local word lines and said potential corresponding to an inactivated state.

Claim 30

The semiconductor memory device according to claim 23, further comprising signal generating means for generating a signal for once simultaneously rendering all of said second switching means included in said plurality of decoder means conductive prior to said operation of said plurality of decoder means.

Claim 31

The semiconductor memory device according to claim 25, wherein said main word line pair includes first and second main word lines, said first main word line receiving said first signal and said second main word line receiving said second signal.

Claim 32

The semiconductor memory device according to claim 28, wherein each of said first switching means includes first conductivity type first transistor means being responsive to said first signal, each of said second switching means includes second conductivity type second transistor means being responsive to said first signal, and each of said third switching means includes third transistor means of said second conductivity type being responsive to said second signal.

Claim 33

The semiconductor memory device according to claim 28, wherein each of said first switching means includes first transistor means being responsive to said first signal, each of said second switching means includes second transistor means having the same conductivity type as that of said first transistor means and being responsive to said second signal, and each of said third switching means includes third transistor means having the same conductivity type as those of said first and second transistor means and being responsive to said first signal.

Claim 34

The semiconductor memory device according to claim 28, wherein each of said first switching means includes first conductivity type first transistor means being responsive to said first signal, each of said second switching means having the same conductivity type as that of said first transistor means and being responsive to said second signal, and each of said third switching means includes third transistor means being responsive to said second signal.

Claim 35

The semiconductor memory device according to claim 22, wherein each of said plurality of decoder means includes: first switching means being rendered conductive when the signal on the corresponding one of said select lines is activated, for applying said first select signal to the corresponding one of said local word lines, and second switching means coupled between said corresponding local word line and a potential corresponding to an inactivated state and being rendered conductive when the signal on said corresponding select line is inactivated.

Claim 36

The semiconductor memory device according to claim 32, each of said plurality of decoder means includes forcing means for forcing the corresponding one of said local word lines to said potential corresponding to an inactivated state when at least one of said corresponding select line and said first select line is inactivated state.

Claim 37

The semiconductor memory device according to claim 33, wherein each of said forcing means is rendered conductive when said first select signal is inactivated, for applying said first select signal to the corresponding one of said local word lines.

Claim 38

The semiconductor memory device according to claim 34, wherein said main word line pair includes first and second main word lines, said main word line receiving said first signal and said second main word line receiving said second signal.

Claim 39

The semiconductor memory device according to claim 35, wherein each of said first switching means includes first conductivity type first transistor means being responsive to the signal on the corresponding one of said select lines and being coupled between said first signal and the corresponding one of said local word lines, each of said second switching means includes second conductivity type second transistor means being responsive to the signal on the corresponding one of said select lines, and each of said third switching means includes third transistor means of said second conductivity type being responsive to said second signal.

Claim 40

The semiconductor memory device according to claim 26, wherein each of said first switching means includes first transistor means being responsive to said second signal, and each of said second switching means includes second transistor means having the same conductivity type as that of said first transistor means and being responsive to said first signal.

Claim 41

The semiconductor memory device according to claim 27, wherein each of said first switching means includes first transistor means being responsive to said first signal, and each of said second switching means includes second transistor means having the same conductivity type as that of said first transistor means and being responsive to said second signal.

Claim 42

A semiconductor memory device comprising: a first memory cell array block including a plurality of memory cells and a plurality of local word lines arranged in a plurality of rows, a second memory cell array block including a plurality of memory cells and a plurality of local word lines arranged in a plurality of rows, said plurality of local word lines in said first memory cell array block and said plurality of local word lines in said second memory cell array corresponding to each other to constitute a plurality of local word line pairs, a first main word line provided corresponding to said first memory cell array block, a second main word line provided corresponding to said second memory cell array block, first selecting means for applying a first select signal to one of said first and second main word lines, a plurality of select lines provided corresponding to said plurality of local word line pairs, second selecting means for applying a second select signal to one of said plurality of select lines, a plurality of first decoder means provided corresponding to said plurality of local word lines in said first memory cell array block, a plurality of second decoder means provided corresponding to said plurality of local word lines in said second memory cell array block, each of said first decoder means activating the corresponding one of said local word lines in said first memory cell array block in response to said first select signal applied to said first main word line and said second select signal applied to said corresponding select lines, each of said plurality of second decoder means activating the corresponding one of said local word lines in the said second memory cell array block in response to said first select signal applied to the said second main word line and said second select signal applied to said corresponding select line.

Claim 43

A semiconductor memory device comprising: a first memory cell array block including a plurality of memory cells and a plurality of local word lines arranged in a plurality of rows, a second memory cell array block including a plurality of memory cells and a plurality of local word lines arranged in a plurality of rows, said plurality of local word lines in said first memory cell array block and said plurality of local word lines in said second memory cell array corresponding to each other to constitute a plurality of local word line pairs, a first main word line provided corresponding to said first memory cell array block, a second main word line provided corresponding to said second memory cell array block, first selecting means for applying a first select signal to one of said first and second main word lines, a plurality of select lines provided corresponding to said plurality of local word line pairs, second selecting means for applying a second select signal to one of said plurality of select lines, a plurality of first decoder means provided corresponding to said plurality of local word lines in said first memory cell array block, a plurality of second decoder means provided corresponding to said plurality of local word lines in said second memory cell array block, each of said first decoder means activating the corresponding one of said local word lines in said first memory cell array block in response to said first select signal applied to said first main word line and said second select signal applied to said corresponding select lines, each of said plurality of second decoder means activating the corresponding one of said local word lines in the said second memory cell array block in response to said first select signal applied to the said second main word line and said second select signal applied to said corresponding select line.

Claim 44

The semiconductor memory device according to claim 39, wherein each of said plurality of first decoder means includes: first switching means being rendered conductive when said first main word line is activated, for applying the signal on the corresponding one of said select lines to the corresponding one of said local word lines in said first block, and second switching means coupled between said corresponding local word line and a potential corresponding to an inactivated state and being rendered conductive when said first main word line is inactivated, each of said plurality of second decoder means includes: third switching means being rendered conductive when said second main word line is activated, for applying the signal on the corresponding one of said select lines to the corresponding one of said local word lines in said second block, and fourth switching means coupled between said corresponding local word line and said potential corresponding to an inactivated state and being rendered conductive when said second main word line is inactivated.

Claim 45

A semiconductor memory device according to claim 40, wherein each of said plurality of first decoder means further includes first forcing means for forcing the potential on said corresponding local word line to said potential corresponding to an inactivated state when at least one of said first main word line and the corresponding one of said select lines is inactivated, and each of said plurality of second decoder means further includes second forcing means for forcing the potential on said corresponding local word line to said potential corresponding to an inactivated state when at least one of said second main word line and the corresponding one of said select lines is inactivated.

Claim 46

The semiconductor memory device according to claim 41, wherein each of said first forcing means includes fifth switching means being rendered conductive when said first main word line is activated, for applying the signal on the corresponding one of said select lines to said corresponding local word line, and each of said second forcing means includes sixth switching means being rendered conductive when said second main word line is activated, for applying the signal on the corresponding one of said select lines to said corresponding local word line.

Claim 47

The semiconductor memory device according to claim 41, wherein each of said first forcing means includes first resistance means coupled between said corresponding local word line and said potential corresponding to an inactivated state, and each of said second forcing means includes second resistance means coupled between said corresponding local word line and said potential corresponding to an inactivated state.

Claim 48

The semiconductor memory device according to claim 40, further comprising signal generating means for generating a signal for once simultaneously rendering conductive all of said second switching means included in said plurality of first decoder means and all of said fourth switching means included in said plurality of second decoder means prior to said operations of said plurality of first decoder means and said plurality of second decoder means.

Claim 49

The semiconductor memory device according to claim 42, wherein said first select signal includes first and second signals complementary to each other, said first main word line includes a first signal line receiving said first signal and a second signal line receiving said second signal, and said second main word line includes a third signal line receiving said first signal and a fourth signal line receiving said second signal.

Claim 50

The semiconductor memory device according to claim 45, wherein each of said first switching means includes first conductivity type first transistor means being responsive to the signal on said first signal line, each of said second switching means includes second conductivity type second transistor means being responsive to the signal on said first signal line, each of said third switching means includes third transistor means of said first conductivity type being responsive to the signal on said third signal line, each of said fourth switching means includes fourth transistor means of said second conductivity type being responsive to the signal on said third signal line, each of said fifth switching means includes fifth transistor means of said second conductivity type being responsive to the signal on said second signal line, and each of said sixth switching means includes sixth transistor means of said second conductivity type being responsive to the signal on said fourth signal line.

Claim 51

The semiconductor memory device according to claim 45, wherein each of said first switching means includes first transistor means being responsive to the signal on said second signal line, each of said second switching means includes second transistor means having the same conductivity type as that of said first transistor means and being responsive to the signal on said first signal line, each of said third switching means includes third transistor means being responsive to the signal on said fourth signal line, each of said fourth switching means includes fourth transistor means having the same conductivity type as that of said third transistor means and being responsive to the signal on said third signal line, each of said fifth switching means includes fifth transistor means having the same conductivity type as those of said first and second transistor means and being responsive to the signal on said second signal line, and each of said sixth switching means includes sixth transistor means having the same conductivity type as those of said first and second transistor means and being responsive to the signal on said fourth signal line.

Claim 52

The semiconductor memory device according to claim 45, wherein each of said first switching means includes first conductivity type first transistor means being responsive to the signal on said first signal line, each of said second switching means includes second transistor means of said first conductivity type being responsive to the signal on said second signal line, each of said third switching means includes third transistor means of said first conductivity type being responsive to the signal on said third signal line, each of said fourth switching means includes fourth transistor means of said first conductivity type being responsive to the signal on said fourth signal line, each of said fifth switching means includes second conductivity type fifth transistor means being responsive to the signal on said second signal line, and each of said sixth switching means includes sixth transistor means of said second conductivity type being responsive to the signal on said fourth signal line.

Claim 53

The semiconductor memory device according to claim 39, wherein each of said plurality of first decoder means includes: first switching means being rendered conductive when the corresponding one of said select lines is activated, for applying the signal on said first main word line to the corresponding one of said local word lines in said first block, and second switching means coupled between said corresponding local word line and a potential corresponding to an inactivated state and being rendered conductive when the corresponding one of said select lines is inactive, each of said plurality of second decoder means includes: third switching means being rendered conductive when the corresponding one of said select lines is activated, for applying the signal on said second main word line to the corresponding one of said local word lines in said second block, and fourth switching means coupled between said corresponding local word line and said potential corresponding to an inactivated state and being rendered conductive when the corresponding one of said select lines is inactivated.

Claim 54

The semiconductor memory device according to claim 49, wherein each of said plurality of first decoder means further includes first forcing means for forcing the potential on said corresponding local word line to said potential corresponding to an inactivated state when at least one of the corresponding one of said select lines and said first main word line is inactivated, and each of said plurality of second decoder means includes second forcing means for forcing the potential on said corresponding local word line to said potential corresponding to an inactivated state when at least one of the corresponding one of said select lines and said second main word line is inactivated.

Claim 55

The semiconductor memory device according to claim 50, wherein each of said first forcing means includes fifth switching means being rendered conductive when the corresponding one of said select lines is inactivated, for applying the signal on said corresponding select line to said corresponding local word line, and each of said second forcing means includes sixth switching means being rendered conductive when the corresponding one of said select lines is inactivated, for applying the signal on said corresponding select line to said corresponding local word line.

Claim 56

The semiconductor memory device according to claim 50, wherein each of said first forcing means includes first resistance means coupled between said corresponding local word line and said potential corresponding to an inactivated state, and each of said second forcing means includes second resistance means coupled between said corresponding local word line and said potential corresponding to an inactivated state.

Claim 57

The semiconductor memory device according to claim 50, further comprising signal generating means for generating a signal for once simultaneously rendering conductive all of said second switching means included in said plurality of first decoder means and all of said fourth switching means included in said plurality of second decoder means prior to said operations of said plurality of first decoder means and said plurality of second decoder means.

Claim 58

The semiconductor memory device according to claim 51, wherein said first select signal includes first and second signals complementary to each other, said first main word line includes a first signal line receiving said first signal and a second signal line receiving said second signal, and said second main word line includes a third signal line receiving said first signal and a fourth signal line receiving said second signal.

Claim 59

The semiconductor memory device according to claim 54, wherein each of said first switching means includes first conductivity type first transistor means being responsive to the signal on the corresponding one of said select lines and coupled between said first signal line and the corresponding one of said local word lines, each of said second switching means includes second conductivity type second transistor means being responsive to the signal on the corresponding one of said select lines, each of said third switching means includes third transistor means of said first conductivity type being responsive to the signal on the corresponding one of said select lines and connected between said third signal line and the corresponding one of said local word lines, each of said fourth switching means includes fourth transistor means of said second conductivity type being responsive to the signal on the corresponding one of said select lines, each of said fifth switching means includes fifth transistor means of said second conductivity type being responsive to the signal on said second signal line, and each of said sixth switching means includes sixth transistor means of said second conductivity type being responsive to the signal on said fourth signal line.

Claim 60

The semiconductor memory device according to claim 43, wherein each of said first switching means includes first conductivity type first transistor means being responsive to the signal on said first main word line, each of said second switching means includes second conductivity type second transistor means being responsive to the signal on said first main word line, each of said third switching means includes third transistor means of said first conductivity type being responsive to the signal on said second main word line, and each of said fourth switching means includes fourth transistor means of said second conductivity type being responsive to the signal on said second main word line.

Claim 61

The semiconductor memory device according to claim 43, wherein said first select signal includes first and second signals complementary to each other, said first main word line includes a first signal line receiving said first signal and a second signal line receiving said second signal, said second main word line includes a third signal line receiving said first signal and a fourth signal line receiving said second signal, each of said first switching means includes first transistor means being responsive to the signal on said first signal line, each of said second switching means includes second transistor means having the same conductivity type as that of said first transistor means and being responsive to the signal on said second signal line, each of said third switching means includes third transistor means being responsive to the signal on said third signal line, and each of said fourth switching means includes fourth transistor means having the same conductivity type as that of said third transistor means and being responsive to the signal on said fourth signal line.

Claim 62

The semiconductor memory device according to claim 44, wherein each of said first switching means includes first conductivity type first transistor means being responsive to the signal on said first main word line, each of said second switching means includes second conductivity type second transistor means being responsive to the signal on said first main word line, each of said third switching means includes third transistor means of said first conductivity type being responsive to the signal on said second main word line, and each of said fourth switching means includes fourth transistor means of said second conductivity type being responsive to the signal on said second main word line.

Claim 63

The semiconductor memory device according to claim 44, wherein said first select signal includes first and second signals complementary to each other, said first main word line includes a first signal line receiving said first signal and a second signal line receiving said second signal, said second main word line includes a third signal line receiving said first signal and a fourth signal line receiving said second signal, each of said first switching means includes first transistor means being responsive to the signal on said first signal line, each of said second switching means includes second transistor means having the same conductivity type as that of said first transistor means and being responsive to the signal on said second signal line, each of said third switching means includes third transistor means being responsive to the signal on said third signal line, and each of said fourth switching means includes fourth transistor means having the same conductivity type as that of said third transistor means and being responsive to the signal on said fourth signal line.

Claim 64

The semiconductor memory device according to claim 52, wherein each of said first switching means includes first conductivity type first transistor means being responsive to the signal on the corresponding one of said select lines and connected between said first main word line and the corresponding one of said local word lines, each of said second switching means includes second conductivity type second transistor means being responsive to the signal on the corresponding one of said select signals, each of said third switching means includes third transistor means of said first conductivity type being responsive to the signal on the corresponding one of said select lines and connected between said second main word line and the corresponding one of said local word lines, and each of said fourth switching means includes fourth transistor means of said second conductivity type being responsive to the signal on the corresponding one of said select lines.

Claim 65

The semiconductor memory device according to claim 53, wherein each of said first switching means includes first conductivity type first transistor means being responsive to the signal on the corresponding one of said select lines and connected between said first main word line and the corresponding one of said local word lines, each of said second switching means includes second conductivity type second transistor means being responsive to the signal on the corresponding one of said select signals, each of said third switching means includes third transistor means of said first conductivity type being responsive to the signal on the corresponding one of said select lines and connected between said second main word line and the corresponding one of said local word lines, and each of said fourth switching means includes fourth transistor means of said second conductivity type being responsive to the signal on the corresponding one of said select lines.

Claim 66

A semiconductor memory device having a decoder responsive to first and second select signals to activate or deactivate a predetermined select signal, said decoder comprising: first, second, third and fourth lines carrying, respectively, the first select signal, the second select signal, the predetermined select signal and a ground potential; first field effect transistor of p-type polarity having source, drain and gate electrodes a second field effect transistor of n-type polarity having source, drain and gate electrodes; the gates being connected to each other and to the second line for receiving said second select line; the source of said second field effect transistor being connected to the fourth line for receiving the ground potential; the source of said first field effect transistor connected to said first line for receiving said first select signal; the drains of said first and second field effect transistors being connected to each other and to said third line for supplying said predetermined select signal; and forcing means for rendering the said second select signal inactive before the first select signal becomes active for decoder operation.

Claim 67

A semiconductor memory device having a decoder responsive to first and second select signals to activate or deactivate a predetermined select signal, said decoder comprising: first, second, third and fourth lines carrying, respectively, the first select signal, the second select signal, the predetermined select signal and a ground potential; first field effect transistor of p-type polarity having source, drain and gate electrodes a second field effect transistor of n-type polarity having source, drain and gate electrodes; the gates being connected to each other and to the second line for receiving said second select line; the source of said second field effect transistor being connected to the fourth line for receiving the ground potential; the source of said first field effect transistor connected to said first line for receiving said first select signal; the drains of said first and second field effect transistors being connected to each other and to said third line for supplying said predetermined select signal; and forcing means for rendering the said second select signal inactive before the first select signal becomes active for decoder operation.