Memory array addressing

Claim 2

A semiconductor memory circuit device comprising: a memory cell array comprising a plurality of memory cells arranged in rows and columns; first means for receiving input row address signals, each of which comprises a predetermined number of bits, said first receiving means providing an output of row address signals; a row decoder circuit which receives said row address signals from said first receiving means and provides output decoded signals for selecting a row from said memory cell array, said row decoder circuit being comprised of a plurality of NAND circuits; a word driver circuit connected between the output of said row decoder circuit and said memory array; second means for receiving input column address signals, each of which comprises a predetermined number of bits, said second receiving means providing an output of column address signals; and a column decoder circuit which receives said column address signals from said second receiving means and provides output decoded signals for selecting a column of said memory array, said column decoder circuit being comprised of a plurality of NOR circuits.

Claim 3

A semiconductor memory circuit device comprising: a memory cell array comprising a plurality of memory cells arranged in rows and columns; first means for receiving input row address signals, each of which comprises a predetermined number of bits, said first receiving means providing an output of at least first partial row address signals, each of which comprises a portion of said predetermined number of bits of a corresponding input row address signal; a first row decoder circuit comprised of a plurality of first unit row decoders, each of which receives said first partial row address signals from said first receiving means and provides intermediate first decoded signals of said first partial address signals, each of said first unit row decoders being comprised of a NAND circuit; a plurality of first inverters; a second row decoder circuit comprised of a plurality of second unit row decoders, each of which selectively receives said first intermediate decoded signals through said first inverters and provides an output decoded signal for selecting a row from said memory cell array, each of said second unit row decoders being comprised of a NAND circuit; a word driver circuit connected between the output of said second row decoder circuit and said memory cell array; second means for receiving input column address signals, each of which comprises a predetermined number of bits, said second receiving means providing an output of at least first partial column address signals, each of which comprises a portion of said predetermined number of bits of a corresponding input column address signal; a first column decoder circuit comprised of a plurality of first unit column decoders, each of which receives said first partial column address signals from said second receiving means and provides second intermediate decoded signals of said first partial column address signals, each of said first unit column decoders being comprised of a NOR circuit; a plurality of second inverters; and a second column decoder circuit comprised of a plurality of second unit column decoders, each of which selectively receives said second intermediate decoded signals through said second inverters and provides output decoded signals for selecting a column of said memory array, each of said second unit column decoders being comprised of a NOR circuit.

Claim 4

A semiconductor memory circuit device comprising: a memory cell array comprising a plurality of memory cells arranged in rows and columns; first means for receiving input row address signals, each of which comprises a predetermined number of bits, said first receiving means providing an output of at least first partial row address signals, each of which comprises a portion of said predetermined number of bits of a corresponding input row address signal; a first row decoder circuit comprised of a plurality of first unit row decoders, each of which receives said first partial row address signals from said first receiving means and provides intermediate first decoded signals of said first partial address signals, each of said first unit row decoders being comprised of a NAND circuit; a plurality of first inverters; a second row decoder circuit comprised of a plurality of second unit row decoders, each of which selectively receives said first intermediate decoded signals through said first inverters and provides an output decoded signal for selecting a row from said memory cell array, each of said second unit row decoders being comprised of a NAND circuit; a word driver circuit connected between the output of said second row decoder circuit and said memory cell array; second means for receiving input column address signals, each of which comprises a predetermined number of bits, said second receiving means providing an output of at least first partial column address signals, each of which comprises a portion of said predetermined number of bits of a corresponding input column address signal; a first column decoder circuit comprised of a plurality of first unit column decoders, each of which receives said first partial column address signals from said second receiving means and provides second intermediate decoded signals of said first partial column address signals, each of said first unit column decoders being comprised of a NOR circuit; a plurality of second inverters; and a second column decoder circuit comprised of a plurality of second unit column decoders, each of which selectively receives said second intermediate decoded signals through said second inverters and provides output decoded signals for selecting a column of said memory array, each of said second unit column decoders being comprised of a NOR circuit.

Claim 5

A semiconductor memory circuit device according to claim 2, wherein each of said unit first row decoders and unit first column decoders is responsive to two bits of said first partial row address signals and first parallel column address signals, respectively.

Claim 6

A semiconductor memory circuit device according to claim 3, wherein for 2-bit input signals made up of bits B X0 , B X1 , B X0 and B X1 , each of said unit first row decoders provides intermediate decoded output signals of MX.sub.0 =B.sub.X0 ·B.sub.X1 MX.sub.1 =B.sub.X0 ·B.sub.X1 MX.sub.2 =B.sub.X0 ·B.sub.X1 MX.sub.3 =B.sub.X0 ·B.sub.X1 and wherein for input signals made up of bits B Y0 , B Y1 , B Y0 and B Y1 , each of said first column unit decoders provides intermediate decoded output signals of: MY.sub.0 =B.sub.Y0 ·B.sub.Y1 MY.sub.1 =B.sub.Y0 ·B.sub.Y1 MY.sub.2 =B.sub.Y0 ·B.sub.Y1 MY.sub.3 =B.sub.Y0 ·B.sub.Y1.

Claim 7

A semiconductor memory circuit device according to claim 2, wherein said first receiving means provides an additional output of second partial row address signals, each of which comprises a different portion of said predetermined number of bits of said corresponding input row address signals than said first partial row address signals, and further comprising a word control circuit coupled between said first receiving means and said word driver circuit, wherein said word control circuit receives said second partial row address signals and controls said word driver circuit in accordance with said second partial row address signals to provide word signals for selecting rows from said memory array.

Claim 8

A semiconductor memory circuit device according to claim 5, wherein said word driver comprises a plurality of unit driver circuits, and wherein the pitch in a column direction between individual memory cells in said memory array is equal to the pitch in a columnar direction between the unit decoder circuits in said second row decoder and the pitch in a columnar direction between unit driver circuits in said word driver circuit.

Claim 9

A semiconductor memory circuit device according to claim 2, wherein each of first and second unit row decoders is comprised of a complementary NAND circuit, and each of said first and second unit column decoders is comprised of a complementary NOR circuit.

Claim 10

A semiconductor memory circuit device according to claim 7, wherein said word driver circuit comprises a plurality of complementary type unit driver circuits, each of said unit driver circuits including a first FET of first conductivity type having a source connected to an output of said word control circuit, a drain connected to said memory cell array and gate connected to the output of said second row decoder circuit, and a second FET of second conducivity type having a source connected to a reference potential point, a drain connected to the drain of said first FET, and a gate commonly connected to the gate of said first FET.

Claim 11

A semiconductor memory circuit device according to claim 8, wherein each of the outputs of said second unit row decoders is connected to at least two unit driver circuits.