Complementary output, high-density CMOS decoder/driver circuit for semiconductor memories

Claim 2

A decoder/driver circuit means for semiconductor memories of the type including a precharge clock, a reset clock and address lines comprising an OR circuit means including AN-1 n-type channel devices having gate electrodes respectively connected to AN-1 address lines and responsive to address bit signals A1 through AN-1 and drain electrodes connected in common, an n-type channel device having a gate electrode connected to a reset clock and responsive to a reset clock signal φR, a p-type channel device having a gate electrode connected to a precharge clock and responsive to a precharge clock signal φPC, and an output node, a one of two selection circuit means connected to said OR circuit means and to AN and AN address lines and responsive to an AN address bit signal and the complement of an AN address bit signal, respectively, thereon, and an output driver stage connected to said selection circuit means, said output driver stage including first and second nodes connected to said selection circuit means, first and second transistor driver circuits connected, respectively, to said first and second nodes, and a first driver output line and a second driver output line connected respectively to said first and second transistor driver circuits, said decoder/driver circuit being responsive to said address bit signals on said A1 through AN address lines for providing an output signal on said first driver output line and said second driver output line in response to said address bit signals.

Claim 3

A decoder/driver circuit according to claim 1 wherein said first driver output line is a word line WLi and said second driver output line is a word line WLi+1.

Claim 4

A decoder/driver circuit according to claim 2 wherein said transistor device having a gate electrode connected to said precharge clock is a p-channel device having a source electrode connected to a voltage source V DD and a drain electrode connected in common with the drain electrodes of said AN-1 transistor devices, and wherein said AN-1 transistor devices are n-channel devices, and

Claim 5

wherein said transistor device having a gate electrode connected to said reset clock is a n-channel device having a drain electrode connected in common with said drain electrodes of said AN-1 transistor devices.

Claim 6

wherein said transistor device having a gate electrode connected to said reset clock is a n-channel device having a drain electrode connected in common with said drain electrodes of said AN-1 transistor devices.

Claim 7

A decoder/driver circuit according to claim 3 wherein said OR circuit means further includes a pair of transistor devices consisting of a p-channel device and an n-channel device, said p-channel device having a source electrode connected to said voltage source V DD and a drain electrode connected to the drain electrode of said n-channel device and to said OR circuit means output node, said pair of transistor devices having gate electrodes connected in common with said drain electrodes of said AN-1 transistor devices.

Claim 8

A decoder/driver circuit according to claim 4 wherein said one of two selection circuit means includes two pairs of transistors, each pair including a p-channel device and an n-channel device, the source electrode of the p-channel device of one of said pairs being connected to said AN address bit line and the source electrode of said p-channel device of said other one of said pairs being connected to said AN address line, the gate electrode of said p and n-channel devices of said two pairs of transistors being connected in common with said output node of said OR circuit means, and the drain electrodes of said p-channel device and the drain electrode of said n-channel device of one of said two transistor pairs being connected in common to said first node of said output driver stage, and the drain electrode of said n-channel device and the drain electrode of said n-channel device of the other one of said two transistor pairs being connected in common to said second node of said output driver stage.

Claim 9

A decoder/driver stage according to claim 5 wherein said output driver stage includes a first two pairs of transistors connected between said first node and said WLi output lead and a second two pairs of transistors connected between said second node and said WLi+1 output lead, said first and second two pairs of transistors each including a p-channel device having a source electrode connected to voltage source V DD and a drain electrode connected to the drain of an n-channel device.

Claim 10

A decoder/driver circuit according to claim 6 wherein the address signal and their complements on lines A1-AN-1 are in a low signal state, and wherein the address bit on line AN goes to a high state thereby applying voltage V DD to said second node of said output driver stage to select and provide a signal on said WLi+1 output line.

Claim 11

A decoder/driver circuit according to claim 6 wherein the address signals and their complements on lines A1-AN-1 are in a low signal state, and wherein the address bit on line AN goes to a high state thereby applying voltage V DD to said first node of said output driver stage to select and provide a signal on said WLi output line.

Claim 12

A decoder/driver circuit for a semiconductor memory comprising: an OR decoder means connected to true and complement lines of a plurality of A1 to AN-1 memory address bits for receiving said memory address bit signals thereon, said OR decoder means further including a first output node means having a low signal condition thereon when all said plurality of designated address bit signals A1 to AN-1 coupled thereto are at a low signal condition and having a high signal condition thereon when any of said plurality of designated address bit signals A1 to AN-1 have a high signal condition, an output word line driver means coupled to a first memory word line and a second memory word line, a selection means coupled to said first output node means of said OR decoder means and the input of said output word line driver means, said selection means being also coupled to the true and complement lines of an AN memory address bit signal, said selection means being responsive to a low signal condition on said OR decoder first output node means and a high signal condition on said true line of said AN address bit signal for producing a high signal condition on said first memory word line and a low signal condition on said second memory word line, said selection means being also responsive to a low signal condition on said OR decoder first output node means and a high signal condition on said complement line of said AN address bit signal for producing a high signal condition on said second memory word line and a low signal condition on said first memory word line, wherein said selection means includes two pairs of transistors, each pair including a p-channel device and an n-channel device, the source electrode of the p-channel device of a first one of said pairs being connected to said AN address bit line and the source electrode of said p-channel device of said other one of said pairs being connected to said AN address line, the gate electrode of said p and n-channel devices of said two pairs of transistors being connected in common with said first output node means of said OR decoder means, and the drain electrodes of said p-channel device and the drain electrode of said n-channel device of one of said two transistor pairs being connected in common to one of two inputs of said output word line driver means, and the drain electrode of said p-channel device and the drain electrode of said n-channel device of the other one of said two transistor pairs being connected in common to the other of said two inputs of said output word line driver means, wherein a high signal condition on said AN address bit line coupled to said first transistor pair and a low signal condition on said OR decoder first output node means produces a high signal condition on said first word line, and wherein a high signal condition on said complement line connected to said second transistor pair and a low signal condition on said OR decoder first output node means produces a high signal condition on said second word line.

Claim 13

A decoder/driver circuit for a semiconductor memory comprising: an OR decoder means connected to true and complement lines of a plurality of A1 to AN-1 memory address bits for receiving said memory address bit signals thereon, said OR decoder means further including a first output node means having a low signal condition thereon when all said plurality of designated address bit signals A1 to AN-1 coupled thereto are at a low signal condition and having a high signal condition thereon when any of said plurality of designated address bit signals A1 to AN-1 have a high signal condition, an output word line driver means coupled to a first memory word line and a second memory word line, a selection means coupled to said first output node means of said OR decoder means and the input of said output word line driver means, said selection means being also coupled to the true and complement lines of an AN memory address bit signal, said selection means being responsive to a low signal condition on said OR decoder first output node means and a high signal condition on said true line of said AN address bit signal for producing a high signal condition on said first memory word line and a low signal condition on said second memory word line, said selection means being also responsive to a low signal condition on said OR decoder first output node means and a high signal condition on said complement line of said AN address bit signal for producing a high signal condition on said second memory word line and a low signal condition on said first memory word line, wherein said selection means includes two pairs of transistors, each pair including a p-channel device and an n-channel device, the source electrode of the p-channel device of a first one of said pairs being connected to said AN address bit line and the source electrode of said p-channel device of said other one of said pairs being connected to said AN address line, the gate electrode of said p and n-channel devices of said two pairs of transistors being connected in common with said first output node means of said OR decoder means, and the drain electrodes of said p-channel device and the drain electrode of said n-channel device of one of said two transistor pairs being connected in common to one of two inputs of said output word line driver means, and the drain electrode of said p-channel device and the drain electrode of said n-channel device of the other one of said two transistor pairs being connected in common to the other of said two inputs of said output word line driver means, wherein a high signal condition on said AN address bit line coupled to said first transistor pair and a low signal condition on said OR decoder first output node means produces a high signal condition on said first word line, and wherein a high signal condition on said complement line connected to said second transistor pair and a low signal condition on said OR decoder first output node means produces a high signal condition on said second word line.

Claim 14

A decoder/driver circuit according to claim 9 wherein said OR decoder means includes a plurality of switching transistors coupled to said true and complement lines of said plurality of A1 to AN-1 memory address bits and wherein a high signal condition on any of the lines connected to said OR decoder produces a charge of said OR decoder first output node means and switches off said selection means, resulting in said first and second word lines remaining low.

Claim 15

A decoder/driver circuit according to claim 10 wherein said OR decoder means further includes a precharge transistor device coupled between a potential voltage supply source and said OR decoder first output node means, and which switches off in response to a precharge clock signal φPC applied to the gate thereof.

Claim 16

A decoder/driver circuit according to claim 11 wherein said OR decoder means further includes a reset transistor device coupled to said decoder output first node means and responsive to a reset signal φR applied to the gate thereof for discharging said OR decoder first output node means.