Abstract This is a vertical MOSFET device with low gate to source overlap capacitance. It can comprise a semiconductor substrate 22 of the first conductivity type, a source region 24,26 of a second conductivity type formed in the upper surface of the substrate 22; a vertical pillar with a channel region 28 of the first conductivity type, a lightly doped drain region 30 of the second conductivity type and a highly doped drain contact region 32 of the second conductivity type; a gate insulator 34, a gate electrode 36 surrounding the vertical pillar, and an insulating spacer 38 between the source 24,26 and a portion of the gate 36 regions. This is also a method of forming a vertical MOSFET device on a single crystal semiconductor substrate, with the device having a pillar on the substrate, with the pillar having a channel region in a lower portion and with the channel region having a top and a highly doped first source/drain region in an upper portion of the pillar, with the substrate having a highly doped second source/drain region and with a gate insulator on the substrate and on the pillar. The method comprises: isotropically forming a first gate electrode material layer on the pillar and the substrate; anisotropically etching the first gate electrode material leaving a vertical portion of gate electrode material on the pillar; anisotropically depositing an insulating spacer; and conformally depositing a second gate electrode material layer.
A vertical FET device with a semiconductor pillar, said device comprising: a. a source region in a semiconductor substrate; b. a channel region in said pillar; c. a drain region in said pillar above said channel region; d. a gate electrode surrounding said pillar, said gate electrode comprising a vertical portion adjacent said channel region and a horizontal extension adjacent said vertical portion; e. a thick insulating spacer over said source region and under said horizontal extension of said gate electrode, said insulating spacer having a vertical sidewall directly contacting and adjacent to part of a vertical side of said vertical portion of said gate electrode; and f. a gate insulator formed directly on said channel region between said gate electrode and said channel region, wherein said thick insulating spacer is substantially thicker than said gate insulator.
Claim 2
Dependent Claim
137 words
A vertical FET device with a semiconductor pillar, said device comprising: a. a source region in a semiconductor substrate; b. a channel region in said pillar; c. a drain region in said pillar above said channel region; d. a gate electrode surrounding said pillar, said gate electrode comprising a vertical portion adjacent said channel region and a horizontal extension adjacent said vertical portion; e. a thick insulating spacer over said source region and under said horizontal extension of said gate electrode, said insulating spacer having a vertical sidewall directly contacting and adjacent to part of a vertical side of said vertical portion of said gate electrode; and f. a gate insulator formed directly on said channel region between said gate electrode and said channel region, wherein said thick insulating spacer is substantially thicker than said gate insulator.
Claim 3
Dependent Claim
24 words
The device of claim 1, wherein said drain region comprises a lightly doped drain region in said pillar below a highly doped drain region.
Claim 4
Dependent Claim
21 words
The device of claim 1, wherein said source region comprises a highly doped source region and a lightly doped source region.
Claim 5
Dependent Claim
23 words
The device of claim 3, wherein said pillar extends over said lightly doped source region but not over said highly doped source region.
Claim 6
Dependent Claim
10 words
The device of claim 1, wherein said substrate is silicon.
Claim 7
Dependent Claim
11 words
The device of claim 1, wherein said insulating spacer is oxide.
Claim 8
Dependent Claim
10 words
The device of claim 1, wherein said gate is polysilicon.
Claim 9
Dependent Claim
18 words
The device of claim 1, wherein said device has a self-aligned etch stop layer above said drain region.