US5495121A
Expired / Lapsed
US
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Semiconductor device
Assignee: Semiconductor Energy Laboratory Co Ltd
•
Filing: 1992-09-30
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Granted: 1996-02-27
•
Expires: 2012-09-30
Abstract
Abstract A semiconductor device or a semiconductor integrated circuit includes a field effect transistor having a source region, a drain region and a channel regions formed within a semiconductor substrate. A lower wiring is formed on the semiconductor substrate to form a gate electrode and its extension and oxidized to form an oxide film covering the lower wiring. An upper wiring is formed over the lower wiring on the semiconductor substrate to make contact with the drain or source region. The lower wiring is electrically insulated from the upper wiring by the oxide film.
Inventors
- 👤 Shunpei Yamazaki
- 👤 Akira Mase
- 👤 Hideki Uochi
- 👤 Yasuhiko Takemura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:52
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10D30/0321; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/6731; H10D30/6737; H10D30/6739; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6745; H10D30/6746; H10D86/00; G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/1333; G02F1/1345; G02F1/13454; G02F1/136; G02F1/1362; G02F1/13624; G02F1/136245
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
118 words
A semiconductor device comprising: a semiconductor layer; a first insulating layer formed on the semiconductor layer, said first insulating layer including a gate insulating layer; a gate electrode formed on the insulating layer; a first wiring formed on said first insulating layer provided on said semiconductor layer, said wiring comprising the same material as said gate electrode and connected to said gate electrode; and a second wiring extending over said first wiring, wherein a surface of said gate electrode and said first wiring is each covered with an anodic oxidation film of said gate electrode and said first wiring, and said second wiring is isolated from said first wiring by the anodic oxidation film of said first wiring.
Claim 2
Dependent Claim
118 words
A semiconductor device comprising: a semiconductor layer; a first insulating layer formed on the semiconductor layer, said first insulating layer including a gate insulating layer; a gate electrode formed on the insulating layer; a first wiring formed on said first insulating layer provided on said semiconductor layer, said wiring comprising the same material as said gate electrode and connected to said gate electrode; and a second wiring extending over said first wiring, wherein a surface of said gate electrode and said first wiring is each covered with an anodic oxidation film of said gate electrode and said first wiring, and said second wiring is isolated from said first wiring by the anodic oxidation film of said first wiring.
Claim 3
Dependent Claim
37 words
The semiconductor device as claimed in claim 1 wherein said gate electrode and said first wiring comprise the same material selected from the group consisting of Ti, Al, Ta, Cr, silicon, WSi 2 and MoSi 2 .
Claim 4
Dependent Claim
27 words
The semiconductor device as claimed in claim 1 further comprising another insulating layer interposed between said second wiring and said anodic oxidation film of said first wiring.
Claim 5
Dependent Claim
40 words
The semiconductor device as claimed in claim 1 wherein said second wiring is connected through at least one contact hole in at least said first insulating layer with at least one of source and drain regions formed within said semiconductor.
Claim 6
Dependent Claim
22 words
The semiconductor device as claimed in claim 1 wherein said gate electrode and said first wiring comprise a phosphorus doped polycrystalline silicon.
Claim 7
Dependent Claim
18 words
The semiconductor integrated circuit as claimed in claim 1 wherein said second insulating layer is a field insulator.
Claim 8
Dependent Claim
40 words
The semiconductor device as claimed in claim 1 wherein said gate electrode comprises a multi-layer of a phosphorus doped silicon film and a silicide film selected from the group consisting of a WSi 2 film and a MoSi 2 film.
Claim 9
Dependent Claim
123 words
A semiconductor device comprising: a gate insulating layer formed on a semiconductor; a gate electrode formed on said gate insulating layer; a channel region formed within said semiconductor below said gate electrode; a pair of first impurity regions formed within said semiconductor between which said channel region is defined, where said first impurity regions are doped with an impurity at a first concentration; and a pair of second impurity regions adjacent to said first impurity regions within said semiconductor where said second impurity regions are doped with the impurity at a second concentration higher than said first concentration, wherein said gate electrode is covered with an oxide layer of said gate electrode and said channel region extends beyond edges of said gate electrode.
Claim 10
Dependent Claim
123 words
A semiconductor device comprising: a gate insulating layer formed on a semiconductor; a gate electrode formed on said gate insulating layer; a channel region formed within said semiconductor below said gate electrode; a pair of first impurity regions formed within said semiconductor between which said channel region is defined, where said first impurity regions are doped with an impurity at a first concentration; and a pair of second impurity regions adjacent to said first impurity regions within said semiconductor where said second impurity regions are doped with the impurity at a second concentration higher than said first concentration, wherein said gate electrode is covered with an oxide layer of said gate electrode and said channel region extends beyond edges of said gate electrode.
Claim 11
Dependent Claim
18 words
The device of claim 8 wherein said oxide layer is an anodic oxidation layer of said gate electrode.
Claim 12
Dependent Claim
13 words
A device as in claim 1 where said semiconductor comprises a semiconductor substrate.
Claim 13
Dependent Claim
18 words
A device as in claim 1 where said semiconductor comprises a semiconductor layer disposed on an insulating surface.
Claim 14
Dependent Claim
13 words
A device as in claim 1 where said device is an integrated circuit.
Claim 15
Dependent Claim
128 words
A semiconductor device comprising: a gate insulating layer formed on a semiconductor layer; a gate electrode formed on said gate insulating layer; a channel region formed within said semiconductor layer below said gate electrode; a pair of first impurity regions formed within said semiconductor layer between which said channel region is defined, where said first impurity regions are doped with an impurity at a first concentration; and a pair of second impurity regions adjacent to said first impurity regions within said semiconductor layer where said second impurity regions are doped with the impurity at a second concentration higher than said first concentration, wherein said gate electrode is covered with an oxide layer of said gate electrode and where said first impurity regions are located under said oxide layer.
Claim 16
Dependent Claim
128 words
A semiconductor device comprising: a gate insulating layer formed on a semiconductor layer; a gate electrode formed on said gate insulating layer; a channel region formed within said semiconductor layer below said gate electrode; a pair of first impurity regions formed within said semiconductor layer between which said channel region is defined, where said first impurity regions are doped with an impurity at a first concentration; and a pair of second impurity regions adjacent to said first impurity regions within said semiconductor layer where said second impurity regions are doped with the impurity at a second concentration higher than said first concentration, wherein said gate electrode is covered with an oxide layer of said gate electrode and where said first impurity regions are located under said oxide layer.
Claim 17
Dependent Claim
22 words
The device of claim 13 wherein said oxide layer of said gate electrode is an anodic oxidation layer of said gate electrode.
Claim 18
Dependent Claim
34 words
The device of claim 13 wherein said gate electrode and said first wiring comprise the same material selected from the group consisting of Ti, Al, Ta, Cr, silicon, WSi 2 and MoSi 2 .
Claim 19
Dependent Claim
24 words
The device of claim 14 further comprising another insulating layer interposed between said second wiring and said anodic oxidation film of said first wiring.
Claim 20
Dependent Claim
131 words
A semiconductor device comprising: a gate insulating layer formed on a semiconductor layer; a gate electrode formed on said gate insulating layer; a channel region formed within said semiconductor layer below said gate electrode; a pair of first impurity regions formed within said semiconductor layer between which said channel region is defined, where said first impurity regions are doped with an impurity at a first concentration; and a pair of second impurity regions adjacent to said first impurity regions within said semiconductor layer where said second impurity regions are doped with the impurity at a second concentration higher than said first concentration, wherein said gate electrode is covered with an oxide layer of said gate electrode and where said channel region extends to but not beyond edges of said gate electrode.
Claim 21
Dependent Claim
131 words
A semiconductor device comprising: a gate insulating layer formed on a semiconductor layer; a gate electrode formed on said gate insulating layer; a channel region formed within said semiconductor layer below said gate electrode; a pair of first impurity regions formed within said semiconductor layer between which said channel region is defined, where said first impurity regions are doped with an impurity at a first concentration; and a pair of second impurity regions adjacent to said first impurity regions within said semiconductor layer where said second impurity regions are doped with the impurity at a second concentration higher than said first concentration, wherein said gate electrode is covered with an oxide layer of said gate electrode and where said channel region extends to but not beyond edges of said gate electrode.
Claim 22
Dependent Claim
22 words
The device of claim 17 wherein said oxide layer of said gate electrode is an anodic oxidation layer of said gate electrode.
Claim 23
Dependent Claim
34 words
The device of claim 17 wherein said gate electrode and said first wiring comprise the same material selected from the group consisting of Ti, Al, Ta, Cr, silicon, WSi 2 and MoSi 2 .
Claim 24
Dependent Claim
24 words
The device of claim 18 further comprising another insulating layer interposed between said second wiring and said anodic oxidation film of said first wiring.
Claim 25
Dependent Claim
145 words
A semiconductor device comprising: a gate insulating layer formed on a semiconductor layer; a gate electrode formed on said gate insulating layer; a channel region formed within said semiconductor layer below said gate electrode; a pair of first impurity regions formed within said semiconductor layer between which said channel region is defined, where said first impurity regions are doped with an impurity at a first concentration; and a pair of second impurity regions adjacent to said first impurity regions within said semiconductor layer where said second impurity regions are doped with the impurity at a second concentration higher than said first concentration, a further insulating layer formed on said semiconductor layer over at least said second impurity regions; wherein said gate electrode is covered with an oxide layer of said gate electrode and where said further insulating layer is thicker than said gate insulating layer.
Claim 26
Dependent Claim
145 words
A semiconductor device comprising: a gate insulating layer formed on a semiconductor layer; a gate electrode formed on said gate insulating layer; a channel region formed within said semiconductor layer below said gate electrode; a pair of first impurity regions formed within said semiconductor layer between which said channel region is defined, where said first impurity regions are doped with an impurity at a first concentration; and a pair of second impurity regions adjacent to said first impurity regions within said semiconductor layer where said second impurity regions are doped with the impurity at a second concentration higher than said first concentration, a further insulating layer formed on said semiconductor layer over at least said second impurity regions; wherein said gate electrode is covered with an oxide layer of said gate electrode and where said further insulating layer is thicker than said gate insulating layer.
Claim 27
Dependent Claim
22 words
The device of claim 21 wherein said oxide layer of said gate electrode is an anodic oxidation layer of said gate electrode.
Claim 28
Dependent Claim
34 words
The device of claim 21 wherein said gate electrode and said first wiring comprise the same material selected from the group consisting of Ti, Al, Ta, Cr, silicon, WSi 2 and MoSi 2 .
Claim 29
Dependent Claim
24 words
The device of claim 22 further comprising another insulating layer interposed between said second wiring and said anodic oxidation film of said first wiring.
Claim 30
Dependent Claim
16 words
The device of claim 21 wherein said channel region extends beyond edges of said gate electrode.
Claim 31
Dependent Claim
19 words
The device of claim 21 wherein said channel region extends to but not beyond edges of said gate electrode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1999-02-26 | 1999-08-28 | 2000-02-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-26 | 2003-08-28 | 2004-02-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-26 | 2007-08-28 | 2008-02-27 | $7700.00 | Window Closed / Lapsed |