MOS memory device having a LDD structure and a visor-like insulating layer

Claim 1

A MOS transistor having a dual gate structure comprising: a semiconductor substrate of a first conductivity type having a major surface, a first gate insulating layer on the major surface of said semiconductor substrate, a first gate electrode formed on said first gate insulating layer and maintained in the electrically floating state, a second gate insulating layer formed on the surface of said first gate electrode and comprised of a laminated structure of first and second insulating layers, a second gate electrode formed on the surface of said second gate insulating layer, and a pair of impurity regions spaced apart from each other on opposite sides of said first gate electrode and defining a channel region in the semiconductor substrate, wherein said first insulating layer of said second gate insulating layer overlies the upper surface and the lateral surface of said first gate electrode, wherein said second insulating layer of said second gate insulating layer overlies the upper and lateral surfaces of said first insulating layer, wherein said pair of impurity regions each comprise a first impurity region of lower concentration and a second impurity region of higher concentration adjoining said first impurity region and spaced further from said channel region, and wherein said first impurity regions of lower concentration partially extend underneath said first gate electrode, and wherein said second impurity regions of higher concentration are self-aligned with said second gate insulating layer.