Process for fabricating insulated-gate field-effect transistors with self-aligned contacts

Claim 2

A process for fabricating metal oxide semiconductor (MOS) field-effect devices having predefined doped active device regions, including: (a) providing a surface passivation layer on the surface of a semiconductor body, (b) forming a high temperature-resistant gate electrode member on the surface of said passivation layer to define one lateral boundary of an active device region, (c) forming a permanent insulating, etch-resistant and impurity barrier mask on the surface of said passivation layer and spaced from said gate electrode member to define another lateral boundary of said active device region, (d) introducing chosen impurities through exposed areas of both sides of said gate electrode member and defined by edges of said gate electrode member and edges of said etch-resistant and impurity barrier mask and into said semiconductor body to form said doped active device regions, (e) removing a portion of said passivation coating which lies over each of said doped regions, and (f) depositing a metallization pattern over a portion of said insulating mask and into electrical contact with said doped regions, whereby said insulating mask serves as an impurity mask to define the lateral dimension of said doped region, as an etch protection mask during the selective removal of portions of said passivation coating, and as a support for said metallization pattern.

Claim 3

The process of claim 1 wherein steps (e) and (f) are combined by using the same resist mask for removing a portion of said passivation coating and for depositing said metallization pattern.

Claim 4

The process of claim 1 wherein said permanent insulating, etch-resistant and impurity barrier mask is selected from the group of materials consisting of silicon nitride, aluminum nitride, aluminum oxide, silicon carbide, titanium oxide, and boron nitride.

Claim 5

The process of claim 1 which includes vapor depositing said insulating, etch-resistant and impurity barrier as a layer of silicon nitride having a thickness between 0.2 to 1.0 micrometers.

Claim 6

The process of claim 1 wherein said high temperature-resistant gate electrode is selected from the group of materials consisting of polysilicon, tungsten, tantalum, molybdenum, platinum, and palladium.

Claim 7

A process for fabricating an insulated-gate field-effect device comprising the steps of: (a) providing a surface passivation layer on the surface of a silicon semiconductor body; (b) forming a high temperature-resistant gate electrode member on a portion of said passivation layer and forming a gate-protection insulating layer over said gate electrode member; (c) depositing a layer of an insulating etch-resistant, impurity barrier material over the surface of said passivation layer and said gate-protection insulating layer; (d) opening holes in said layer of insulating etch-resistant, impurity barrier material; (e) introducing conductivity-type-determining impurity ions into the surface of said semiconductor body and through areas thereon unmasked by said gate electrode member and by said impurity barrier material to form ion implanted regions of like conductivity type in said semiconductor body adjacent the region thereof under said refractory gate electrode member, said ion implanted regions forming the source and drain regions of said field-effect device; (f) forming a photoresist pattern having openings over said gate electrode member, over said regions of like conductivity type and said passivation layer thereon, and also over the remaining portion of said insulating material; (g) opening holes in the portions of said passivation layer which are exposed by said openings in step (f) and which lie over portions of said regions of like conductivity type and also opening a hole in a portion of said gate-protection layer which is exposed by said opening in step (f) and which lies over said gate member; and (h) providing electrical connections to said regions of like conductivity type through said holes in said passivation layer and to said gate electrode member through said hole in said gate-protection layer.

Claim 8

A process for fabricating an insulated-gate field-effect device comprising the steps of: (a) providing a surface passivation layer on the surface of a silicon semiconductor body; (b) forming a high temperature-resistant gate electrode member on a portion of said passivation layer and forming a gate-protection insulating layer over said gate electrode member; (c) depositing a layer of an insulating etch-resistant, impurity barrier material over the surface of said passivation layer and said gate-protection insulating layer; (d) opening holes in said layer of insulating etch-resistant, impurity barrier material; (e) introducing conductivity-type-determining impurity ions into the surface of said semiconductor body and through areas thereon unmasked by said gate electrode member and by said impurity barrier material to form ion implanted regions of like conductivity type in said semiconductor body adjacent the region thereof under said refractory gate electrode member, said ion implanted regions forming the source and drain regions of said field-effect device; (f) forming a photoresist pattern having openings over said gate electrode member, over said regions of like conductivity type and said passivation layer thereon, and also over the remaining portion of said insulating material; (g) opening holes in the portions of said passivation layer which are exposed by said openings in step (f) and which lie over portions of said regions of like conductivity type and also opening a hole in a portion of said gate-protection layer which is exposed by said opening in step (f) and which lies over said gate member; and (h) providing electrical connections to said regions of like conductivity type through said holes in said passivation layer and to said gate electrode member through said hole in said gate-protection layer.

Claim 9

The process of claim 6, wherein step (h) includes depositing metal directly over said photoresist pattern of step (f) and then lifting off said photoresist.

Claim 10

In a process for fabricating a self-aligned gate field-effect transistor wherein a semiconductor body is provided with a surface passivation layer and a gate electrode thereon which serves as part of an impurity mask for defining and limiting one lateral dimension of source and drain regions in said body, the improvement comprising: forming an insulating etch-resistant and impurity barrier mask on said surface passivation layer and having one edge portion coextensive and aligned with another lateral dimension of said source and drain regions of said transistor, using said insulating mask to provide part of an impurity mask for said source and drain regions, then part of an etch mask for said passivation layer to expose said source and drain regions for electrical contacts, and finally as a means for supporting a metallization pattern extending thereover and into electrical contact with said source and drain regions, to provide self-aligned electrical contact openings within the lateral boundaries of said source and drain regions of said transistor.

Claim 11

In a process for fabricating a self-aligned gate field-effect transistor wherein a semiconductor body is provided with a surface passivation layer and a gate electrode thereon which serves as part of an impurity mask for defining and limiting one lateral dimension of source and drain regions in said body, the improvement comprising: forming an insulating etch-resistant and impurity barrier mask on said surface passivation layer and having one edge portion coextensive and aligned with another lateral dimension of said source and drain regions of said transistor, using said insulating mask to provide part of an impurity mask for said source and drain regions, then part of an etch mask for said passivation layer to expose said source and drain regions for electrical contacts, and finally as a means for supporting a metallization pattern extending thereover and into electrical contact with said source and drain regions, to provide self-aligned electrical contact openings within the lateral boundaries of said source and drain regions of said transistor.