Multiple-level metallization for integrated circuits
Abstract
Abstract A method of forming multi-level metallization in integrated circuits with essentially zero effective lateral spacing between adjacent isolated metal portions. Indentations are formed at least partially through a first dielectric layer; and a second dielectric layer having apertures registered with and smaller than the indentations is formed thereover such that portions of the second layer overhang the indentations at the perimeters thereof. A thin metal layer then is deposited over the surface of the structure. Because the second dielectric layer overhangs the indentations, the deposited metal is discontinuous at the perimeter of each of the indentations if the deposited metal layer is kept sufficiently thin. Selective connection of adjacent metal portions at any portion of the perimeter of any indentation is made by any of a variety of techniques, such as electroless plating of gold through a photoresist mask.
Inventors
- 👤 C Berglund
- 👤 H Waggener
- 👤 E Nicollian
- 👤 M Tompsett
Bibliographic Details
Claims Analysis
Total Claims: 0References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
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| 3.5 Years (Year 4) | 1977-09-23 | 1978-03-25 | 1978-09-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-09-23 | 1982-03-25 | 1982-09-24 | $3760.00 | Window Closed / Lapsed |
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