Patent CA490551A successfully refreshed from Google Patents.
Patent US5484738A successfully refreshed from Google Patents.
US5484738A
Expired / Lapsed
US
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Method of forming silicon on oxide semiconductor device structure for BiCMOS integrated circuits
Assignee: International Business Machines Corp
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Filing: 1995-03-01
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Granted: 1996-01-16
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Expires: 2015-03-01
Abstract
Abstract A bonded, SOI wafer which has stepped isolation trenches and sublayer interconnections first formed in a bulk silicon wafer. After these process steps are complete, a thin polysilicon layer is formed on the planarized upper surface of the bulk silicon wafer. This thin polysilicon layer is then bound to an oxide layer on the surface of a separate wafer to form a bonded silicon-on-oxide structure. The entire assembly is, in effect inverted, and what had been the lower surface of the bulk silicon wafer, is removed to the bottom of the deepest trench step. In this bonded SOI structure, regions between the trenches are deep and suitable for bipolar device fabrication, while the trench steps form shallow regions suitable for fabrication of CMOS devices.
Inventors
- 👤 Shao-Fu S. Chu
- 👤 Chang-Ming Hsieh
- 👤 Louis L. C. Hsu
- 👤 Kyong-Min Kim
- 👤 Shaw-Ning Mei
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 13:00
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10P90/1914; H10W; H10W10/00; H10W10/10; H10W10/181; Y; Y10; Y10S; Y10S148/00; Y10S148/01; Y10S148/011; Y10S148/012; Y10S148/05; Y10S148/151
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
171 words
A method of fabricating a silicon-on-oxide integrated circuit structure with bipolar and MOS device regions in said structure, comprising the steps: forming a plurality of isolation trenches in a semiconductor wafer extending from one surface of said wafer into said wafer, certain ones of said isolation trenches extending to a first depth in said wafer and certain others of said isolation trenches extending into said wafer to a second depth in said wafer that is less than said first depth; forming a silicon layer on said one surface after said isolation trenches have been formed; forming a reach-through region for bipolar collector contact; forming sub-collector and interconnect regions in said silicon layer; bonding said silicon layer to an oxide layer formed on the surface of a wafer substrate; planarizing the other surface of said semiconductor wafer so that said isolation trenches that extend to said first depth extend to said planarized surface and there is a gap between said isolation trenches that extend to said second depth and said planarized surface.
Claim 2
Independent Claim
171 words
A method of fabricating a silicon-on-oxide integrated circuit structure with bipolar and MOS device regions in said structure, comprising the steps: forming a plurality of isolation trenches in a semiconductor wafer extending from one surface of said wafer into said wafer, certain ones of said isolation trenches extending to a first depth in said wafer and certain others of said isolation trenches extending into said wafer to a second depth in said wafer that is less than said first depth; forming a silicon layer on said one surface after said isolation trenches have been formed; forming a reach-through region for bipolar collector contact; forming sub-collector and interconnect regions in said silicon layer; bonding said silicon layer to an oxide layer formed on the surface of a wafer substrate; planarizing the other surface of said semiconductor wafer so that said isolation trenches that extend to said first depth extend to said planarized surface and there is a gap between said isolation trenches that extend to said second depth and said planarized surface.
Claim 3
Dependent Claim
37 words
A method of fabricating a silicon-on-oxide integrated circuit structure as in claim 1, including the further step of forming a reach-through region in said semiconductor wafer in order to form a collector contact for a bipolar device.
Claim 4
Dependent Claim
23 words
A method of fabricating a silicon-on-oxide integrated circuit structure as in claim 1, wherein said planarizing step is carried out by chemical-mechanical polishing.
Claim 5
Dependent Claim
55 words
A method of fabricating a silicon-on-oxide integrated circuit structure as in claim 1, including the further steps of: forming a field effect device in said gap between said isolation trenches that extend to said second depth anti said planarized surface; and forming a bipolar transistor between said isolation trenches that extend to said first depth.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-15 | 1999-07-17 | 2000-01-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-15 | 2003-07-17 | 2004-01-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-15 | 2007-07-17 | 2008-01-16 | $7700.00 | Window Closed / Lapsed |