US5164218A
Expired / Lapsed
US
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Semiconductor device and a method for producing the same
Assignee: Denso Corp
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Filing: 1991-07-17
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Granted: 1992-11-17
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Expires: 2011-07-17
Abstract
Abstract A semiconductor device of vertical arrangement includes an anode region formed of a first semiconductor substrate and a second semiconductor substrate joined with the first semiconductor substrate. The first semiconductor substrate forms a high-resistance layer with a predetermined impurity density, and the second semiconductor substrate forms a low-resistance layer whose impurity density is higher than that of the high-resistance layer. A PN junction is formed inside the first semiconductor substrate. The periphery of the first semiconductor substrate including the PN junction is configured in an inverted mesa structure and coated with an insulation material. With this arrangement, the semiconductor device has a high withstand voltage and enables an employment of a large diameter wafer.
Inventors
- 👤 Kazuhiro Tsuruta
- 👤 Mitutaka Katada
- 👤 Seiji Fujino
- 👤 Masami Yamaoka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:36
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D10/00; H10D10/01; H10D10/051; H10D10/056; H10D10/40; H10D12/00; H10D12/411; H10D12/441; H10D30/01; H10D30/021; H10D30/028; H10D30/0291; H10D62/00; H10D62/10; H10D62/102; H10D62/103; H10D62/104; H10P; H10P10/00; H10P10/12; H10P10/128; H10P54/00; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/019; H10W10/061; H10W10/10; H10W10/181; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10W10/021; H10W10/20; Y; Y10; Y10S; Y10S148/00; Y10S148/012
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
142 words
A method of manufacturing a semiconductor device, comprising: a first process of forming mesa grooves each opening on a mirror-polished surface of a first semiconductor substrate and each of said mesa grooves having side walls inclined at angles; a second process of directly joining the mirror-polished surface of the first semiconductor substrate to a mirror-polished surface of a second semiconductor substrate, thereby forming a joined substrate; a third process of coating walls of a space defined in the joined substrate by oblique side walls of the mesa grooves of the first semiconductor substrate and by the mirror-polished surface of the second semiconductor substrate, with an insulation material layer; and a fourth process of forming a PN junction in the first semiconductor substrate of the joined substrate in a location such that edges of the PN junction are on the oblique side walls.
Claim 2
Independent Claim
142 words
A method of manufacturing a semiconductor device, comprising: a first process of forming mesa grooves each opening on a mirror-polished surface of a first semiconductor substrate and each of said mesa grooves having side walls inclined at angles; a second process of directly joining the mirror-polished surface of the first semiconductor substrate to a mirror-polished surface of a second semiconductor substrate, thereby forming a joined substrate; a third process of coating walls of a space defined in the joined substrate by oblique side walls of the mesa grooves of the first semiconductor substrate and by the mirror-polished surface of the second semiconductor substrate, with an insulation material layer; and a fourth process of forming a PN junction in the first semiconductor substrate of the joined substrate in a location such that edges of the PN junction are on the oblique side walls.
Claim 3
Dependent Claim
35 words
A method according to claim 1, wherein the third process is a process of heat-treating the joined substrate to coat the walls of the space defined in the joined substrate with a thermal oxidation film.
Claim 4
Dependent Claim
31 words
A method according to claim 1, further comprising a fifth process to be executed after the fourth process, of dicing the joined substrate along the mesa grooves to form separate chips.
Claim 5
Dependent Claim
52 words
A method according to claim 1, further comprising a fifth process of forming element portions on a main surface of the first semiconductor substrate, and a sixth process of dicing the joined substrate along the mesa grooves to form separate chips, the fifth and sixth processes being executed after the fourth process.
Claim 6
Dependent Claim
18 words
A method according to claim 1, wherein the third process is executed between the fifth and sixth processes.
Claim 7
Dependent Claim
18 words
A method as in claim 1 wherein said first and second semiconductor substrates are formed of monocrystalline silicon.
Claim 8
Dependent Claim
38 words
A method as in claim 1 comprising the further step of coating walls of the space in the joint substrate with an insulation film which is one of a silicon nitride film and a semi-insulation polycrystalline silicon film.
Claim 9
Dependent Claim
36 words
A method as in claim 1 comprising the further step of coating walls of the space defined in the joint substrate with a multi-layer film formed of a thermal oxidation film and another insulation material film.
Claim 10
Dependent Claim
17 words
A method as in claim 8 wherein said other material insulation film is a silicon nitride film.
Claim 11
Dependent Claim
63 words
A method as in claim 1 wherein said side faces are inclined such that an electric field intensity at a periphery of the PN junction and an electric field intensity on an interface between the high resistance layer and the low resistance layer in the region are each smaller than an electric field intensity voltage at a central area of the PN junction.
Claim 12
Dependent Claim
32 words
A method as in claim 10 wherein an angle of inclination of each of the oblique sides walls is between 0° and 45° with respect to a perpendicular of the PN junction.
Claim 13
Independent Claim
223 words
A method of forming a semiconductor device, comprising the steps of: forming a recess in a region on a mirror-polished surface of a first semiconductor substrate, the recess opening to the mirror-polished surface; forming a plurality of mesa grooves on the periphery of the recess and at a position spaced apart from the periphery by a distance, each of the mesa grooves having oblique side walls and a depth deeper than that of the recess; coating the surface on which the recess and mesa grooves have been made with an insulation material, and filling the recess and mesa grooves with a filler material; mirror-polishing the surface applied with the filler material to expose another area of the mirror-polished surface of the first semiconductor substrate; joining the mirror-polished surface of the first semiconductor substrate with a mirror-polished surface of a second semiconductor substrate, thereby forming a joined substrate; polishing a non-mirror-polished surface of the first semiconductor substrate to expose the mesa grooves; and forming at least one isolated region in the first semiconductor substrate on the second semiconductor substrate in the joined substrate, the isolated region being defined by the mesa grooves and the recess and electrically insulated from the other regions by the insulation material and filler material, and forming functional elements having different functions in the at least one isolated regions, respectively.
Claim 14
Independent Claim
223 words
A method of forming a semiconductor device, comprising the steps of: forming a recess in a region on a mirror-polished surface of a first semiconductor substrate, the recess opening to the mirror-polished surface; forming a plurality of mesa grooves on the periphery of the recess and at a position spaced apart from the periphery by a distance, each of the mesa grooves having oblique side walls and a depth deeper than that of the recess; coating the surface on which the recess and mesa grooves have been made with an insulation material, and filling the recess and mesa grooves with a filler material; mirror-polishing the surface applied with the filler material to expose another area of the mirror-polished surface of the first semiconductor substrate; joining the mirror-polished surface of the first semiconductor substrate with a mirror-polished surface of a second semiconductor substrate, thereby forming a joined substrate; polishing a non-mirror-polished surface of the first semiconductor substrate to expose the mesa grooves; and forming at least one isolated region in the first semiconductor substrate on the second semiconductor substrate in the joined substrate, the isolated region being defined by the mesa grooves and the recess and electrically insulated from the other regions by the insulation material and filler material, and forming functional elements having different functions in the at least one isolated regions, respectively.
Claim 15
Dependent Claim
18 words
A method as in claim 12 wherein said first and second semiconductor substrates are formed of monocrystalline silicon.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-17 | 1996-05-18 | 1996-11-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-17 | 2000-05-18 | 2000-11-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-17 | 2004-05-18 | 2004-11-17 | $7700.00 | Window Closed / Lapsed |