Techniques for via formation and filling

Claim 1

A semiconductor device, comprising: a substrate; a first structure-containing layer, overlying the substrate, containing first structures requiring inter-connection through first subsequently formed vias from a higher level; a first insulating layer overlying the first structure-containing layer; a second structure-containing layer overlying the first insulating layer, disposed at a higher level than the first structure-containing layer, and containing second structures requiring inter-connection through second subsequently formed vias from the higher level; a second insulating layer overlying the second structure-containing layer; and planarized metal filling the second and first vias and making contact from the higher level to the second and first structures, respectively; wherein: the second vias are shallow vias formed through the second insulating layer to the second structures; the first vias are deep vias formed through the second insulating layer and through the first insulating layer to the first structures; and any excess metal initially over-filling the vias is subsequently removed by polishing.