Decoupled refresh on local and system busses in a PC/at or similar microprocessor environment

Claim 1

In a computer having a first memory connected to a first bus connected to a CPU and a second memory connected to a second bus connected to said CPU, a memory refresh device comprising: first means for receiving a refresh request signal and generating in response thereto a first signal indicating that at least one refresh request for said first memory is pending, for generating a third signal in lieu of said first signal when a first predetermined number of refresh requests for said first memory are pending, and for generating a fifth signal in lieu of both said first and third signals when a third predetermined number, larger than said first predetermined number, of refresh requests for said first memory are pending; first responsive means responsive to said first signal for causing a refresh operation of said first memory to be performed as said first memory becomes available for refresh and responsive to said third signal for causing a refresh operation of said first memory to be performed in prolongation of a current access of said first memory without the first bus being relinquished for a subsequent access; second means for receiving said refresh request signal and generating in response thereto a second signal indicating that at least one refresh request for said second memory is pending, for generating a fourth signal in lieu of said second signal when a second predetermined number of refresh requests for said second memory are pending, and for generating a sixth signal in lieu of both said second and fourth signals when a fourth predetermined number, larger than said second predetermined number, of refresh requests for said second memory are pending; second responsive means responsive to said second signal for causing a refresh operation of said second memory to be performed as said second memory becomes available and responsive to said fourth signal for causing a refresh operation of said second memory to be performed in prolongation of a current access of said second memory without the bus being relinquished for a subsequent access; and means connected to said CPU and responsive to assertion of either of said fifth signal or said sixth signal for requesting that said CPU be placed in a hold state while said first and second responsive means cause said first and second memories to be refreshed.