Dynamic memory refresh circuit

Claim 2

A memory refresh circuit for use in a computer system having a central processing unit and a dynamic memory including memory cells requiring periodic refreshing, said memory refresh circuit comprising, means for producing refresh request signals at predetermined intervals; means responsive to said refresh request signals for storing said request signals; means responsive to stored refresh request signals and responsive to a memory access by said central processing unit for starting a memory refresh cycle; and means responsive to the end of a refresh cycle and to said stored refresh request signals for immediately starting another memory refresh cycle so that refresh cycles are continuously performed until a refresh cycle has been performed for each stored refresh request signal.

Claim 3

A memory refresh circuit according to claim 1 wherein said refreshing means comprises means responsive to each of said stored refresh requests for designating one set of memory cells to be refreshed and means for changing said designation after said set has been refreshed.

Claim 4

A memory refresh circuit according to claim 2 further comprising means responsive to said stored refresh requests for continually refreshing said memory cell sets until a memory cell set has been refreshed for each stored refresh request.

Claim 5

A memory refresh circuit according to claim 1 further comprising means responsive to a predetermined number of stored refresh requests for generating an interrupt request to said central processing unit so that said central processing unit causes a memory access to occur in said memory.

Claim 6

A memory refresh circuit for use in a computer system having a central processing unit and a dynamic memory including memory cells requiring periodic refreshing, said memory refresh circuit comprising, means for producing refresh request signals at predetermined intervals; means responsive to said refresh request signals for storing said request signals; means responsive to a predetermined number of stored refresh requests for forcing initiation of a memory access by said central processing unit; means responsive to stored refresh request signals and responsive to said memory access by said central processing unit for starting a memory refresh cycle; and means responsive to the end of a refresh cycle and to said stored refresh request signals for immediately starting another memory refresh cycle so that refresh cycles are continuously performed until a refresh cycle has been peformed for each stored refresh request signal.

Claim 7

A memory refresh circuit for use in a computer system having a central processing unit and a dynamic memory including memory cells requiring periodic refreshing, said memory refresh circuit comprising, means for producing refresh request signals at predetermined intervals; means responsive to said refresh request signals for storing said request signals; means responsive to a predetermined number of stored refresh requests for forcing initiation of a memory access by said central processing unit; means responsive to stored refresh request signals and responsive to said memory access by said central processing unit for starting a memory refresh cycle; and means responsive to the end of a refresh cycle and to said stored refresh request signals for immediately starting another memory refresh cycle so that refresh cycles are continuously performed until a refresh cycle has been peformed for each stored refresh request signal.

Claim 8

A memory refresh circuit according to claim 5 wherein said forcing means comprises means responsive to stored refresh request signals and responsive to a memory access by said central processing unit for refreshing said memory once for each stored refresh request signal, and means responsive to said predetermined number of stored refresh requests for generating an interrupt request to said central processing unit so that said central processing unit causes a memory access to occur in said memory.

Claim 9

A memory refresh circuit according to claim 6 wherein said refreshing means comprises means responsive to each of said stored refresh requests for designating one set of memory cells to be refreshed and means for changing said designation after said set has been refreshed.

Claim 10

A memory refresh circuit according to claim 7 further comprising means responsive to said stored refresh requests for continually refreshing said memory cell sets until a memory cell set has been refreshed for each stored refresh request.

Claim 11

A memory refresh circuit for use in a computer system having a central processing unit and a dynamic memory including memory cells requiring periodic refreshing, said memory refresh circuit comprising, a timer for producing refresh request signals at predetermined intervals; a counter; means responsive to said refresh request signals for incrementing said counter in response to each refresh request signal; means responsive to a non-zero count in said counter and to a memory access by said central processing unit for starting a memory refresh cycle; means responsive to the end of a memory refresh cycle for decrementing said counter; and means responsive to the end of a refresh cycle and to a non-zero count in said counter for immediately starting another memory refresh cycle so that refresh cycles are continuously performed until said counter reaches a zero count.

Claim 12

A memory refresh circuit for use in a computer system having a central processing unit and a dynamic memory including memory cells requiring periodic refreshing, said memory refresh circuit comprising, a timer for producing refresh request signals at predetermined intervals; a counter; means responsive to said refresh request signals for incrementing said counter in response to each refresh request signal; means responsive to a non-zero count in said counter and to a memory access by said central processing unit for starting a memory refresh cycle; means responsive to the end of a memory refresh cycle for decrementing said counter; and means responsive to the end of a refresh cycle and to a non-zero count in said counter for immediately starting another memory refresh cycle so that refresh cycles are continuously performed until said counter reaches a zero count.

Claim 13

A memory refresh circuit according to claim 9 further comprising means responsive to a predetermined count in said counter for initiating an interrupt request to said central processing unit so that said central processing unit causes a memory access to occur in said memory.

Claim 14

A memory refresh circuit according to claim 10 wherein said refreshing means comprises means responsive to a non-zero count in said counter for designating one row of memory cells to be refreshed and means for changing said designation after said row has been refreshed.

Claim 15

A memory refresh circuit according to claim 11 wherein said refreshing means further comprises means responsive to a non-zero count in said counter for decrementing said counter after each row of memory cells has been refreshed.

Claim 16

A memory refresh circuit according to claim 12 further comprising means responsive to a non-zero count in said counter for continually refreshing said memory cell rows until the count in said counter has been decremented to zero.

Claim 17

A memory refresh circuit according to claim 13 wherein said central processing unit generates control signals indicating a memory access and said means for refreshing said memory in response to a memory access by said central processing unit comprises means startable to generate a plurality of timing signals at predetermined intervals and means responsive to said central processing unit control signals for starting said timing means.

Claim 18

A memory refresh circuit according to claim 14 wherein said means for refreshing said memory in response to a memory access by said central processing unit further comprises means responsive to one of said plurality of timing signals and to the count in said counter for generating a refresh signal when said count is non-zero.

Claim 19

A memory refresh circuit according to claim 15 wherein said means for refreshing said memory in response to a memory access by said central processing unit further comprises means responsive to said refresh signal and to another of said plurality of timing signals for restarting said timing means.

Claim 20

A memory refresh circuit for use in a computer system having a central processing unit including circuitry for generating a plurality of control signals indicating a memory access and a dynamic memory including memory cells requiring periodic refreshing, said memory refresh circuit comprising, a timer controlled by said central processing unit for producing refresh request signals at predetermined intervals; a refresh request counter; means responsive to said refresh request signals for incrementing said refresh request counter in response to each refresh request signal; a refresh address counter for generating a plurality of refresh address signals specifying a particular memory cell row in said memory to be refreshed; timing means startable to generate a plurality of timing signals at predetermined intervals; means responsive to said central processor unit control signals for starting said timing means; means responsive to timing signals generated by said timing means for disconnecting said memory from said central processing unit; means responsive to said timing signals for refreshing the memory cell row specified by said refresh address signals; means responsive to a non-zero count in said refresh request counter for decrementing said refresh request counter and for incrementing said refresh address counter after said specified row of memory cells has been refreshed; means responsive to a non-zero count in said refresh request counter and responsive to another of said plurality of timing signals for immediately restarting said timing means so that rows of memory cells are continuously refreshed until the count in said refresh request counter has been reduced to zero; and means responsive to said timing signals and to a zero count in said refresh request counter for reconnecting said memory to said central processing unit.

Claim 21

A memory refresh circuit for use in a computer system having a central processing unit including circuitry for generating a plurality of control signals indicating a memory access and a dynamic memory including memory cells requiring periodic refreshing, said memory refresh circuit comprising, a timer controlled by said central processing unit for producing refresh request signals at predetermined intervals; a refresh request counter; means responsive to said refresh request signals for incrementing said refresh request counter in response to each refresh request signal; a refresh address counter for generating a plurality of refresh address signals specifying a particular memory cell row in said memory to be refreshed; timing means startable to generate a plurality of timing signals at predetermined intervals; means responsive to said central processor unit control signals for starting said timing means; means responsive to timing signals generated by said timing means for disconnecting said memory from said central processing unit; means responsive to said timing signals for refreshing the memory cell row specified by said refresh address signals; means responsive to a non-zero count in said refresh request counter for decrementing said refresh request counter and for incrementing said refresh address counter after said specified row of memory cells has been refreshed; means responsive to a non-zero count in said refresh request counter and responsive to another of said plurality of timing signals for immediately restarting said timing means so that rows of memory cells are continuously refreshed until the count in said refresh request counter has been reduced to zero; and means responsive to said timing signals and to a zero count in said refresh request counter for reconnecting said memory to said central processing unit.

Claim 22

A memory refresh circuit according to claim 17 further comprising means responsive to a predetermined count in said counter for initiating an interrupt request to said central processing unit so that said central processing unit causes a memory access to occur in said memory.