Semiconductor memory device

Claim 2

A semiconductor memory device receiving a selection signal, comprising: a plurality of row lines; a plurality of column lines, each of said column lines having two ends; a plurality of storage cells, operatively connected to one of said row lines and one of said column lines; a plurality of gate means, each having first and second ends, each of the first ends of said gate means operatively connected to one of the ends of said column lines, for controlling connections to said column lines; a plurality of sense amplifiers disposed along both ends of said column lines, each operatively connected to the second end of one of said gate means, and comprising first and second groups of sense amplifiers; and a selection circuit, operatively connected to said gate means for controlling said gate means in response to the selection signal to connect a selected group of said column lines via selected gate means to the first group of said sense amplifiers for accessing information in selected storage cells and to connect an unselected group of said column lines via unselected gate means to the second group of said sense amplifiers for performing only a refresh operation on unselected storage cells operatively connected to the unselected group of said column lines.

Claim 3

A semiconductor memory device as claimed in claim 1, wherein said gate means comprise bidirectional transfer gate elements, each of said bidirectional transfer gate elements operatively connected to one of said column lines, one of said sense amplifiers and said selection circuit.

Claim 4

A semiconductor memory device as claimed in claim 2, wherein each of said bidirectional transfer gate elements comprises a field effect transistor having a gate operatively connected to said selection circuit and source and drain regions operatively connected between one of said column lines and one of said sense amplifiers.

Claim 5

A semiconductor memory device as claimed in claim 3, wherein said storage cells having a writing voltage and said selection circuit provides a selection voltage higher than the writing voltage of said storage cells to the gate of each of said field effect transistors in the selected gate means.

Claim 6

A semiconductor memory device as claimed in claim 1, wherein each of said sense amplifiers comprises bistable and active pull-up circuits operatively connected to one of said gate means.

Claim 7

A semiconductor memory device as claimed in claim 1, wherein each of said storage cells comprises: a field effect transistor, operatively connected to one of said column lines, having a gate operatively connected to one of said row lines; and a capacitor, operatively connected to said field effect transistor.

Claim 8

A semiconductor memory device as claimed in claim 1, wherein said semiconductor memory device receives row address data and the selection signal is a part of the row address data.

Claim 9

A semiconductor memory device receiving row and column addresses and a selection signal, comprising: a plurality of row lines having ends; a plurality of pairs of column lines, each of said column lines having first and second ends; a plurality of storage cells, each of said storage cells operatively connected to one of said row lines and one of said column lines; a plurality of gate means disposed along the first and second ends of said column lines, each of said gate means having a first end operatively connected to one of the ends of the pairs of said column lines and a second end, for controlling connections to said column lines; a plurality of sense amplifiers disposed along the first and second ends of said column lines, each operatively connected to the second end of one of said gate means, and comprising first and second groups of sense amplifiers; row decoder means, disposed along and operatively connected to the ends of said row lines and operatively connected to receive the row address, for selecting one of said row lines in dependence upon the row address; column decoder means, disposed along the first end of said column lines and operatively connected to the first group of said sense amplifiers and to receive the column address, for selecting among said pairs of column lines in dependence upon the column address; and a selection circuit, operatively connected to said gate means and to receive the selection signal, for switching said gate means in response to the selection signal to connect selected pairs of column lines via selected gate means to the first group of said sense amplifiers for accessing information in selected storage cells and to connect unselected pairs of column lines via unselected gate means to the second group of said sense amplifiers for performing only a refresh operation on unselected storage cells connected to the unselected pairs of column lines.

Claim 10

A semiconductor memory device receiving row and column addresses and a selection signal, comprising: a plurality of row lines having ends; a plurality of pairs of column lines, each of said column lines having first and second ends; a plurality of storage cells, each of said storage cells operatively connected to one of said row lines and one of said column lines; a plurality of gate means disposed along the first and second ends of said column lines, each of said gate means having a first end operatively connected to one of the ends of the pairs of said column lines and a second end, for controlling connections to said column lines; a plurality of sense amplifiers disposed along the first and second ends of said column lines, each operatively connected to the second end of one of said gate means, and comprising first and second groups of sense amplifiers; row decoder means, disposed along and operatively connected to the ends of said row lines and operatively connected to receive the row address, for selecting one of said row lines in dependence upon the row address; column decoder means, disposed along the first end of said column lines and operatively connected to the first group of said sense amplifiers and to receive the column address, for selecting among said pairs of column lines in dependence upon the column address; and a selection circuit, operatively connected to said gate means and to receive the selection signal, for switching said gate means in response to the selection signal to connect selected pairs of column lines via selected gate means to the first group of said sense amplifiers for accessing information in selected storage cells and to connect unselected pairs of column lines via unselected gate means to the second group of said sense amplifiers for performing only a refresh operation on unselected storage cells connected to the unselected pairs of column lines.

Claim 11

A semiconductor memory device as claimed in claim 8, wherein said gate means comprise bidirectional transfer gate elements, each of said bidirectional transfer gate elements operatively connected to one of said column lines, one of said sense amplifiers and said selection circuit.

Claim 12

A semiconductor memory device as claimed in claim 9, wherein each of said bidirectional transfer gate elements comprises a field effect transistor having a gate operatively connected to said selection circuit and source and drain regions operatively connected between one of said column lines and one of said sense amplifiers.

Claim 13

A semiconductor memory device as claimed in claim 10, wherein said storage cells have a writing voltage and said selection circuit provides a voltage higher than the writing voltage of said storage cells to the gate of each of said field effect transistors in the selected gate means.

Claim 14

A semiconductor memory device as claimed in claim 8, wherein each of said sense amplifiers comprises bistable and active pull-up circuits operatively connected to one of said gate means.

Claim 15

A semiconductor memory device as claimed in claim 8, wherein each of said storage cells comprises: a field effect transistor, operatively connected to one of said column lines and one of said row lines; and a capacitor operatively connected to said field effect transistor.

Claim 16

A semiconductor memory device as claimed in claim 8 and receiving row address data, wherein the selection signal and the row address are received together as the row address data.

Claim 17

A semiconductor memory device receiving row and column addresses and a selection signal, comprising: a plurality of row lines having ends; a plurality of pairs of column lines intersecting said row lines at intersections thereof, each of said column lines having first and second ends; a plurality of storage cells, each of said storage cells operatively connected to one of said row lines and one of said column lines at the intersection thereof; a plurality of gate means disposed along both ends of said column lines, each operatively connected to one of the ends of the pairs of said column lines, for controlling connections to said column lines; a plurality of sense amplifiers disposed along both ends of said column lines, each of said sense amplifiers operatively connected to said gate means and operatively connectable to two pairs of said column lines via said gate means; row decoder means disposed along and operatively connected to the ends of said row lines and operatively connected to receive the row address, for selecting one of said row lines in dependence upon the row address; column decoder means, disposed along the first ends of said column lines and operatively connected to said sense amplifiers disposed along the first ends of said column lines and to receive the column address, for selecting among said pairs of column lines in dependence upon the column address; and a selection circuit, operatively connected to said gate means and to receive a portion of the row address, for switching said gate means in dependence upon the portion of the row address to connect selected pairs of column lines via selected gate means to said sense amplifiers disposed along the first ends of said column lines for accessing information in a selected storage cell, and to connect pairs of column lines via unselected gate means to said sense amplifiers disposed along the second ends of said column lines for performing only a refresh operation on unselected storage cells.

Claim 18

A semiconductor memory device receiving row and column addresses and a selection signal, comprising: a plurality of row lines having ends; a plurality of pairs of column lines intersecting said row lines at intersections thereof, each of said column lines having first and second ends; a plurality of storage cells, each of said storage cells operatively connected to one of said row lines and one of said column lines at the intersection thereof; a plurality of gate means disposed along both ends of said column lines, each operatively connected to one of the ends of the pairs of said column lines, for controlling connections to said column lines; a plurality of sense amplifiers disposed along both ends of said column lines, each of said sense amplifiers operatively connected to said gate means and operatively connectable to two pairs of said column lines via said gate means; row decoder means disposed along and operatively connected to the ends of said row lines and operatively connected to receive the row address, for selecting one of said row lines in dependence upon the row address; column decoder means, disposed along the first ends of said column lines and operatively connected to said sense amplifiers disposed along the first ends of said column lines and to receive the column address, for selecting among said pairs of column lines in dependence upon the column address; and a selection circuit, operatively connected to said gate means and to receive a portion of the row address, for switching said gate means in dependence upon the portion of the row address to connect selected pairs of column lines via selected gate means to said sense amplifiers disposed along the first ends of said column lines for accessing information in a selected storage cell, and to connect pairs of column lines via unselected gate means to said sense amplifiers disposed along the second ends of said column lines for performing only a refresh operation on unselected storage cells.

Claim 19

A semiconductor memory device as claimed in claim 15, wherein said gate means comprise bidirectional transfer gate elements, each of said bidirectional transfer gate elements operatively connected to one of said column lines, one of said sense amplifiers and said selection circuit.

Claim 20

A semiconductor memory device as claimed in claim 16, wherein each of said bidirectional transfer gate elements comprises a field effect transistor having a gate operatively connected to said selection circuit and source and drain regions operatively connected between one of said column lines and one of said sense amplifiers.

Claim 21

A semiconductor memory device as claimed in claim 17, wherein said storage cells have a writing voltage and said selection circuit provides a voltage higher than the writing voltage of said storage cells to the gate of each of said field effect transistors in the selected gate means.

Claim 22

A semiconductor memory device as claimed in claim 15, wherein each of said sense amplifiers comprises bistable and active pull-up circuits operatively connected to one of said gate means.

Claim 23

A semiconductor memory device as claimed in claim 15, wherein each of said storage cells comprises: a field effect transistor operatively connected to one of said column lines and one of said row lines; and a capacitor operatively connected to said field effect transistor.

Claim 24

A semiconductor memory device receiving row and column addresses, comprising: a memory cell array having first and second sides and storage cells therein; first gate means, adjacent to the first side of said memory cell array and operatively connected to the storage cells, for selecting a portion of the storage cells; second gate means, adjacent to the second side of said memory cell array and operatively connected to the storage cells, for selecting the remainder of the storage cells; a first group of sense amplifiers, adjacent and operatively connected to said first gate means, for accessing the portion of the storage cells; a second group of sense amplifiers, adjacent and operatively connected to said second gate means, for performing a refresh operation on the remainder of the storage cells; a row address decoder operatively connected to said memory cell array; a column decoder, adjacent and operatively connected to said first group of sense amplifiers, for selecting a sense amplifier in dependence upon the column address; selection means, receiving part of the row address and operatively connected to said first and second gate means, for controlling said first and second gate means in dependence upon the part of the row address.

Claim 25

A semiconductor memory device receiving row and column addresses, comprising: a memory cell array having first and second sides and storage cells therein; first gate means, adjacent to the first side of said memory cell array and operatively connected to the storage cells, for selecting a portion of the storage cells; second gate means, adjacent to the second side of said memory cell array and operatively connected to the storage cells, for selecting the remainder of the storage cells; a first group of sense amplifiers, adjacent and operatively connected to said first gate means, for accessing the portion of the storage cells; a second group of sense amplifiers, adjacent and operatively connected to said second gate means, for performing a refresh operation on the remainder of the storage cells; a row address decoder operatively connected to said memory cell array; a column decoder, adjacent and operatively connected to said first group of sense amplifiers, for selecting a sense amplifier in dependence upon the column address; selection means, receiving part of the row address and operatively connected to said first and second gate means, for controlling said first and second gate means in dependence upon the part of the row address.