Threshold adjustment in vertical DMOS devices

Claim 2

A field effect transistor comprising: a body region situated in a semiconductor body along a major surface thereof, a first PN junction being formed between the semiconductor body and the body region; a source situated in the body region along said surface, a second PN junction spaced apart from the first PN junction being formed between the body region and the source; a drain situated in the semiconductor body along said surface and extending to meet the body region; and a gate comprising a conductive gate layer disposed over said surface and electrically insulated from the semiconductor body, the conductive gate layer lying over at least part of the body region between the first and second PN junctions to electrostatically control conduction in a threshold adjusted channel of the body region at a specified operational condition of the transistor, a threshold adjust dopant being vertically localized generally in the channel, the threshold adjust dopant also being present in the semiconductor body laterally outside the body region, the threshold adjust dopant having a peak concentration whose depth into the semiconductor body below said surface is nonuniform laterally along said surface.

Claim 3

A transistor as in claim 1 wherein the depth of the peak concentration of the threshold adjust dopant has a greater value in the source than in the channel.

Claim 4

A transistor as in claim 2 wherein the peak concentration of the threshold adjust dopant within the channel lies in a layer generally parallel to said surface.

Claim 5

A transistor as in claim 3 wherein the threshold adjust dopant is of the same conductivity type as the source and drain.

Claim 6

A transistor as in claim 4 wherein the source and drain are p type.

Claim 7

A transistor as in claim 3 wherein the threshold adjust dopant is present at a concentration for establishing both a positive threshold at a zero gate bias and an off-condition of the transistor at a gate bias within the specified operational condition of the transistor.

Claim 8

A transistor as in claim 3 wherein the threshold adjust dopant is present at a concentration for establishing both a negative threshold at a zero gate bias and an off-condition of the transistor at a gate bias within the specified operational condition of the transistor.

Claim 9

A transistor as in claim 1 wherein a portion of the body region is more heavily doped than the remainder of the body region and extends into the semiconductor body to a greater distance than said remainder of the body region.

Claim 10

A transistor as in claim 1 wherein the semiconductor body comprises a substrate and an overlying epitaxial layer that consists largely of semiconductor material of the same conductivity type as the substrate but doped to a lighter level than the substrate.

Claim 11

A transistor as in claim 9 wherein the drain comprises the substrate and material of the epitaxial layer outside the body region.

Claim 12

A structure created from a semiconductor body having a major surface, the structure comprising a pair of like-polarity field effect transistors each comprising: a body region situated in the semiconductor body along said surface, a first PN junction being formed between the semiconductor body and the body region;. a source situated in the body region along said surface, a second PN junction spaced apart from the first PN junction being formed between the body region and the source; a drain situated in the semiconductor body along said surface and extending to meet the body region; and a gate comprising a conductive gate layer disposed over said surface and electrically insulated from the semiconductor body, the conductive gate layer lying over at least part of the body region between the first and second PN junctions to electrostatically control conduction in a threshold adjusted channel of the body region at a specified operational condition of the transistor; wherein a threshold adjust dopant is vertically localized generally in the channels, the threshold adjust dopant also being present in the semiconductor body laterally outside the body regions, the drains being continuous with each other to form a common drain in which the threshold adjust dopant is present in a region extending fully between the first PN junctions of the transistors, and wherein the threshold adjust dopant has a peak concentration whose depth into the semiconductor body below said surface is non-uniform laterally along said surface.

Claim 13

A structure created from a semiconductor body having a major surface, the structure comprising a pair of like-polarity field effect transistors each comprising: a body region situated in the semiconductor body along said surface, a first PN junction being formed between the semiconductor body and the body region;. a source situated in the body region along said surface, a second PN junction spaced apart from the first PN junction being formed between the body region and the source; a drain situated in the semiconductor body along said surface and extending to meet the body region; and a gate comprising a conductive gate layer disposed over said surface and electrically insulated from the semiconductor body, the conductive gate layer lying over at least part of the body region between the first and second PN junctions to electrostatically control conduction in a threshold adjusted channel of the body region at a specified operational condition of the transistor; wherein a threshold adjust dopant is vertically localized generally in the channels, the threshold adjust dopant also being present in the semiconductor body laterally outside the body regions, the drains being continuous with each other to form a common drain in which the threshold adjust dopant is present in a region extending fully between the first PN junctions of the transistors, and wherein the threshold adjust dopant has a peak concentration whose depth into the semiconductor body below said surface is non-uniform laterally along said surface.

Claim 14

A structure as in claim 11 wherein the depth of the peak concentration of the threshold adjust dopant has a greater value in the sources than in the channels.

Claim 15

A structure as in claim 12 wherein the peak concentration of the threshold adjust dopant within each channel lies in a layer generally parallel to said surface.

Claim 16

A structure as in claim 13 wherein the threshold adjust dopant is of the same conductivity type as the sources and drains.

Claim 17

A structure as in claim 14 wherein the sources and drains are p type.

Claim 18

A structure as in claim 13 wherein the semiconductor body comprises a substrate and an overlying epitaxial layer that consists largely of semiconductor material of the same conductivity type as the substrate but doped to a lighter level than the substrate.

Claim 19

A field effect device as in claim 16 wherein the common drain comprises the substrate and material of the epitaxial layer outside the body regions.

Claim 20

An enhancement-mode field effect transistor comprising: a body region situated in a semiconductor body along a major surface thereof, a first PN junction being formed between the semiconductor body and the body region; a source situated in the body region along said surface, a second PN junction spaced apart from the first PN junction being formed between the body region and the source; a drain situated in the semiconductor body along said surface and extending to meet the body region; and a gate comprising a conductive gate layer disposed over said surface and electrically insulated from the semiconductor body, the conductive gate layer lying over at least part of the body region between the first and second PN junctions to electrostatically control conduction in a threshold adjusted channel of the body region at a specified operational condition of the transistor, a threshold adjust dopant being vertically localized generally in the channel at a non-zero doping level low enough to enable the transistor to operate in the enhancement mode, the threshold adjust dopant also being present in the semiconductor body laterally outside the body region and having a peak concentration whose depth into the semiconductor body below said surface is non-uniform laterally along said surface.

Claim 21

An enhancement-mode field effect transistor comprising: a body region situated in a semiconductor body along a major surface thereof, a first PN junction being formed between the semiconductor body and the body region; a source situated in the body region along said surface, a second PN junction spaced apart from the first PN junction being formed between the body region and the source; a drain situated in the semiconductor body along said surface and extending to meet the body region; and a gate comprising a conductive gate layer disposed over said surface and electrically insulated from the semiconductor body, the conductive gate layer lying over at least part of the body region between the first and second PN junctions to electrostatically control conduction in a threshold adjusted channel of the body region at a specified operational condition of the transistor, a threshold adjust dopant being vertically localized generally in the channel at a non-zero doping level low enough to enable the transistor to operate in the enhancement mode, the threshold adjust dopant also being present in the semiconductor body laterally outside the body region and having a peak concentration whose depth into the semiconductor body below said surface is non-uniform laterally along said surface.

Claim 22

A transistor as in claim 18 wherein the depth of the peak concentration of the threshold adjust dopant has a greater value in the source than in the channel.

Claim 23

A transistor as in claim 19 wherein the peak concentration of the threshold adjust dopant within the channel lies in a layer generally parallel to said surface.

Claim 24

A transistor as in claim 18 wherein the threshold adjust dopant is of the same conductivity type as the source and drain.