Phase clocked latch having both parallel and shunt connected switches for transmission gates

Claim 1

A semiconductor device, comprising: a unit latch circuit consisting of a pair of half-latch circuits, and a control signal supplier processing a clock signal after first and second processing periods of time to produce and apply respective first and second control signals substantially identical in pulse width with the clock signal for applying the first and second control signals to each of said unit latch circuits; wherein said second processing period of time is equal to or longer than and said first processing period of time; each of said pair of half-latch circuits including (a) an input terminal and an output terminal, (b) a first switch connected to said input terminal for turning on or off in the control of said second control signal, (c) first signal transmitting means having an input end connected through said first switch to said input terminal and an output end connected to said output terminal, for practicing a logic inversion, and (d) second signal transmitting means having an input end connected to an output end of said first signal transmitting means and an output end connected to an input end of said first signal transmitting means, for, in accordance with said first control signal, outputting a feedback signal which is obtained by practicing a logic inversion to an output from said first signal transmitting means, wherein said control signal supplier further produces and applies a third control signal, which has a negative logic relation with said first control signal, to said half-latch circuits; said second signal transmitting means including (d-3) a signal processing unit having an input end connected to said input end of said second signal transmitting means and a pair of output ends either of which receives said feedback signal, and (d-4) a second switch having a pair of input ends connected to said pair of output ends of said signal processing unit and an output end for selectively outputting said feedback signal; wherein (d-4-1) said second switch includes first and second unit switches connected in series between said pair of input ends of said second switch for operating in accordance with signals which are opposite in phase to each other, (d-4-2) said first and second unit switches are connected commonly to said output end of said second signal transmitting means, (d-4-3) said first unit switch turning on and off in the control of said first control signal, and (d-4-4) said second unit switch turning on and off in the control of said third control signal; and wherein said control signal supplier further produces and applies a fourth control signal, which has a negative logic relation with said second control signal, to said half-latch circuits; (b-1) said first switch including third and fourth unit switches connected in parallel with each other to operate in accordance with signals which are opposite in phase to each other, (b-2) said third unit switch turning on and off in the control of said second control signal, and (b-3) said fourth unit switch turning on and off in the control of said fourth signal.