Easily and quickly testable master-slave flipflop circuit

Claim 1

A master/slave flipflop comprising: a master flipflop including a first logic gate having an input for receiving an input signal, and a second logic gate having an input connected to an output of said first logic gate, and a first switch means connected between an output of said second logic gate and said input of said first logic gate; a slave flipflop including a third logic gate having an input for receiving an output signal of said master flipflop, and a fourth logic gate having an input connected to an output of said third logic gate, and a second switch means connected between an output of said fourth logic gate and said input of said third logic gate, said output of said third logic gate being coupled to an output node of said master/slave flipflop; a third switch means connected between said output of said first logic gate and said input of said third logic gate; a fourth switch means connected between said output of said second logic gate and said input of said third logic gate; and control means for controlling said first to fourth switch means operates in a normal operating mode to provide clocking to the master/slave flipflop and in a test mode to bring said first to third switch means into an off condition and also to bring said fourth switch means into an on condition so that all said first to fourth logic gates are cascaded.