Low power shift register circuit

Claim 1

A low power shift register circuit for outputting signals corresponding to an input signal according to a clock signal supplied thereto, comprising: a plurality of flip-flops connected in cascade, each of said flip-flops having a data input terminal for receiving a data signal, said input signal being supplied to a data input terminal of one of said flip-flops at a first stage and data input terminals of the other of said flip-flops receiving output signals from a previous one of said flip-flops respectively, each of said flip-flops latching data on the data input terminal in synchronous with the clock signal supplied thereto; and a plurality of clock controlling means, each of said clock controlling means connected to receive said clock signal for controlling an input of said clock signal to respective ones of said flip-flops based on a difference between logic levels of the output signals of said respective ones of said flip-flops and said data signal applied to the data input terminal of said respective ones of said flip-flops so as to prevent the clock signal from being input in a case that the applied data is equal to the level of the output signals and save power consumption, each of said clock controlling means includes first gate means connected to receive said clock signal for selectively passing said clock signal, so that said clock signal is supplied to said respective ones of said flip-flops through said first gate means without an inverter being required for supplying the clock signal to said flip-flops.