Shift register circuit

Claim 2

A shift register circuit comprising: a series circuit comprising a plurality of first clocked gate inverters and inverters which are alternately connected in series, a first one of said first clocked gate inverters being adapted to receive an input pulse signal; an output line connected to an output of each of said inverters for outputting an output pulse signal; and a second clocked gate inverter connected to the output of each of said inverters for outputting an output pulse signal, said first clocked gate inverters operating responsive to a first clock signal, said second clocked gate inverters operating responsive to a second clock signal which is a mutually different frequency from said first clock signal.

Claim 3

The shift register circuit as claimed in claim 1 wherein said second clock signal has a frequency n times that of said first clock signal, where n is an arbitrary integer.

Claim 4

A shift register circuit comprising: a series circuit comprising a plurality of first clocked gate inverters and inverters which are alternately connected in series, a first one of said first clocked gate inverters being adapted to receive an input pulse signal; a second clocked gate inverter connected to an output of each of said first clocked gate inverters for outputting an output pulse signal; and an output line connected to an output of each of said inverters for outputting an output pulse signal, said first clocked gate inverters operating responsive to a first clock signal, said second clocked gate inverters operating responsive to a second clock signal which is a mutually different frequency from said first clock signal.

Claim 5

A shift register circuit comprising: a series circuit comprising a plurality of first clocked gate inverters and inverters which are alternately connected in series, a first one of said first clocked gate inverters being adapted to receive an input pulse signal; a second clocked gate inverter connected to an output of each of said first clocked gate inverters for outputting an output pulse signal; and an output line connected to an output of each of said inverters for outputting an output pulse signal, said first clocked gate inverters operating responsive to a first clock signal, said second clocked gate inverters operating responsive to a second clock signal which is a mutually different frequency from said first clock signal.

Claim 6

The shift register circuit as claimed in claim 3 wherein said second clock signal has a frequency n times that of said first clock signal, where n is an arbitrary integer.

Claim 7

The shift register circuit as claimed in claim 3 which further comprises a third clocked gate inverter which is connected to an output of each of said second clocked gate inverters for outputting an output pulse signal, said third clocked gate inverter operating responsive to a third clock signal which is different from said first and second clock signals.

Claim 8

A shift register circuit comprising: a series circuit comprising a plurality of first clocked gate inverters and inverters which are alternately connected in series, a first one of said first clocked gate inverters being adapted to receive an input pulse signal; a second clocked gate inverter connected to an output of each of said first clocked gate inverters; and a first output line connected to an output of each of said inverters; and first through nth inverter circuits respectively provided in first through nth levels, said first inverter circuit comprising a third clocked gate inverter and a second output line which are connected to an output of said second clocked gate inverter, an ith inverter circuit comprising a third clocked gate inverter and a second output line which are connected to an output of the third clocked gate inverter which is provided in the (i-1)th level and a third clocked gate inverter and a second output line which are connected to the second output line which is provided in the (i-1)th level, said third clocked gate inverters and said second output lines which are provided in the nth level outputting output pulse signals; said first clocked gate inverters operating responsive to a first clock signal, said second clocked gate inverters operating responsive to a second clock signal which is different from said first clock signal, said third clocked gate inverters respectively operating responsive to third clock signals which are dependent on the level in which the third clocked gate inverters are provided and different from said first and second clock signals.

Claim 9

A shift register circuit comprising: a series circuit comprising a plurality of first clocked gate inverters and inverters which are alternately connected in series, a first one of said first clocked gate inverters being adapted to receive an input pulse signal; a second clocked gate inverter connected to an output of each of said first clocked gate inverters; and a first output line connected to an output of each of said inverters; and first through nth inverter circuits respectively provided in first through nth levels, said first inverter circuit comprising a third clocked gate inverter and a second output line which are connected to an output of said second clocked gate inverter, an ith inverter circuit comprising a third clocked gate inverter and a second output line which are connected to an output of the third clocked gate inverter which is provided in the (i-1)th level and a third clocked gate inverter and a second output line which are connected to the second output line which is provided in the (i-1)th level, said third clocked gate inverters and said second output lines which are provided in the nth level outputting output pulse signals; said first clocked gate inverters operating responsive to a first clock signal, said second clocked gate inverters operating responsive to a second clock signal which is different from said first clock signal, said third clocked gate inverters respectively operating responsive to third clock signals which are dependent on the level in which the third clocked gate inverters are provided and different from said first and second clock signals.

Claim 10

The shift register circuit as claimed in claim 6 wherein said first, second and third clock signals have mutually different frequencies, and said third clock signals have frequencies which are different for each level of said inverter circuits.

Claim 11

The shift register circuit as claimed in claim 7 wherein said second clock signal has a frequency n times that of said first clock signal, and said third clock signal has a frequency m times that of said first clock signal, where n and m are arbitrary integers.

Claim 12

The shift register circuit as claimed in claim 6 wherein said first, second and third clock signals have the same frequency but mutually different pulse widths, and said third clock signals have pulse widths which are different for each level of said inverter circuits.

Claim 13

The shift register circuit as claimed in claim 6 which further comprises a 2-input gate which is connected to an output of each of said first through third clocked gate inverters, and said 2-input gate receives a clock signal identical to that received by the clocked gate inverter from which said 2-input gate also receives a signal.

Claim 14

A shift register circuit comprising: a series circuit comprising a plurality of first clocked gate inverters and inverters which are alternatively connected in series, a first one of said first clocked inverters being adapted to receive an input pulse signal; a second clocked gate inverter connected to an output of each of said first clocked gate inverters for outputting an output pulse signal; a third clocked gate inverter which is connected to an output of each of said second clocked gate inverters for outputting an output pulse signal; an output line connected to an output of each of the said inverters for outputting an output pulse signal; and wherein said first clocked gate inverters operate in response to a first clocked signal, said second clocked gate inverters operate in response to a second clocked signal which is different from said first clocked signal, and said third clock gate inverter operate in response to a third clocked signal which is different from said first and second clocked signals.

Claim 15

A shift register circuit comprising: a series circuit comprising a plurality of first clocked gate inverters and inverters which are alternatively connected in series, a first one of said first clocked inverters being adapted to receive an input pulse signal; a second clocked gate inverter connected to an output of each of said first clocked gate inverters for outputting an output pulse signal; a third clocked gate inverter which is connected to an output of each of said second clocked gate inverters for outputting an output pulse signal; an output line connected to an output of each of the said inverters for outputting an output pulse signal; and wherein said first clocked gate inverters operate in response to a first clocked signal, said second clocked gate inverters operate in response to a second clocked signal which is different from said first clocked signal, and said third clock gate inverter operate in response to a third clocked signal which is different from said first and second clocked signals.

Claim 16

The shift register circuit as claimed in claim 11 wherein said second and third clock signals have frequencies which are integral multiples of a frequency of said first clock signal.