Racefree CMOS clocked logic circuit

Claim 2

A racefree CMOS clocked logic circuit comprising: first clocked circuit means including means for providing an input signal and being responsive to said input signal and to a first clock pulse, for selectively transferring said input signal according to said first clock pulse, to provide an interstage signal corresponding to said input signal, said first clocked circuit means including: a first CMOS clocked gate responsive to said input signal and being clocked by a clock pulse corresponding to said first clock pulse for providing said interstage signal, a second CMOS clocked gate being responsive to a first signal and to an inverted clock pulse, said inverted clock pulse being antiphasic to said first clock pulse for selectively and phase-invertedly transferring said first signal according to said inverted clock pulse to provide a second signal, a CMOS logic gate coupled to said second CMOS clocked gate for selectively transferring said second signal to provide said input signal; and second clocked circuit means coupled to said first clocked circuit means and being responsive to said interstage signal and to a second clock pulse for selectively transferring said interstage signal according to said second clock pulse to provide an output signal corresponding to said interstage signal, said second clock pulse being in-phase with said first clock pulse, said second clocked circuit means including: a third CMOS clocked gate responsive to said interstage signal and being clocked by a clock pulse corresponding to said second clock pulse for providing said output signal.

Claim 3

A clocked logic circuit according to claim 1, wherein said first, second and third CMOS clocked gates are inverters.

Claim 4

A clocked logic circuit according to claim 1, wherein said first CMOS clocked gate comprises: a first MOSFET of a first semiconductor type having a source coupled to a positive power source, a gate responsive to an inverted clock pulse which is antiphasic to said first clock pulse and a drain; a second MOSFET of a first semiconductor type having a source coupled to the drain of said first MOSFET, a gate responsive to said input signal and a drain for generating said interstage signal; a third MOSFET of a second semiconductor type having a drain coupled to the drain of said second MOSFET, a gate responsive to said input signal and a source; a fourth MOSFET of a second semiconductor type having a drain coupled to the source of said third MOSFET, a gate responsive to said clock pulse and a source coupled to a negative power source, and wherein said third CMOS clocked gate comprises: a fifth MOSFET of a first semiconductor type having a source coupled to said positive power source, a gate responsive to said inverted clock pulse and a drain; a sixth MOSFET of a first semiconductor type having a source coupled to the drain of said fifth MOSFET, a gate responsive to said interstage signal and a drain for generating said output signal; a seventh MOSFET of a second semiconductor type having a drain coupled to the drain of said sixth MOSFET, a gate responsive to said interstage signal and a source; an eighth MOSFET of a second semiconductor type having a drain coupled to the source of said seventh MOSFET, a gate responsive to said clock pulse and a source coupled to said negative power source.

Claim 5

A racefree CMOS clocked logic circuit comprising: first clocked circuit means including means for providing an input signal and being responsive to said input signal and to a first clock pulse, for selectively transferring said input signal according to said first clock pulse, to provide an interstage signal corresponding to said input signal, said first clocked circuit means including: a first CMOS clocked gate responsive to said input signal and being clocked by a clock pulse corresponding to said first clock pulse for providing said interstage signal, a second CMOS clocked logic gate being responsive to a first signal and an inverted clock pulse, said inverted clock pulse being antiphasic to said first clock pulse for selectively transferring said first signal according to said inverted clock pulse to provide said input signal; and second clocked circuit means coupled to said first clocked circuit means and being responsive to said interstage signal and to a second clock pulse for selectively transferring said interstage signal according to said second clock pulse to provide an output signal corresponding to said interstage signal and a further second signal, said second clock pulse being in-phase with said first clock pulse, said second clocked circuit means including: a third CMOS gate responsive to said interstage signal and being clocked by a clock pulse corresponding to said second clock pulse and providing said output signal, a fourth CMOS clocked gate responsive to said output signal and to said inverted clock pulse for selectively transferring said output signal according to said inverted clock pulse to provide said second signal.

Claim 6

A racefree CMOS clocked logic circuit comprising: first clocked circuit means including means for providing an input signal and being responsive to said input signal and to a first clock pulse, for selectively transferring said input signal according to said first clock pulse, to provide an interstage signal corresponding to said input signal, said first clocked circuit means including: a first CMOS clocked gate responsive to said input signal and being clocked by a clock pulse corresponding to said first clock pulse for providing said interstage signal, a second CMOS clocked logic gate being responsive to a first signal and an inverted clock pulse, said inverted clock pulse being antiphasic to said first clock pulse for selectively transferring said first signal according to said inverted clock pulse to provide said input signal; and second clocked circuit means coupled to said first clocked circuit means and being responsive to said interstage signal and to a second clock pulse for selectively transferring said interstage signal according to said second clock pulse to provide an output signal corresponding to said interstage signal and a further second signal, said second clock pulse being in-phase with said first clock pulse, said second clocked circuit means including: a third CMOS gate responsive to said interstage signal and being clocked by a clock pulse corresponding to said second clock pulse and providing said output signal, a fourth CMOS clocked gate responsive to said output signal and to said inverted clock pulse for selectively transferring said output signal according to said inverted clock pulse to provide said second signal.

Claim 7

A racefree CMOS clocked logic circuit comprising: first clocked circuit means including means for providing an input signal and being responsive to said input signal and to a first clock pulse, for selectively transferring said input signal according to said first clock pulse to provide an interstage signal corresponding to said input signal, said first clocked circuit means including: a first CMOS clocked gate responsive to said input signal and being clocked by an inverted clock pulse corresponding to said first clock pulse for providing said interstage signal, a second CMOS clocked gate being responsive to a first signal and a noninverted clocked pulse, said noninverted clock pulse being antiphasic to said inverted clock pulse for selectively transferring said first signal according to said noninverted clock pulse to provide a second signal, a first CMOS nonclocked logic gate having an input terminal coupled to said second CMOS clocked gate for transferring said second signal to provide said input signal, a third CMOS clocked gate coupled to said first CMOS nonclocked logic gate and being responsive to said input signal and to said inverted clock pulse for selectively transferring said input signal according to said inverted clock pulse to provide a third signal which is fed back to the input terminal of said first CMOS nonclocked logic gate; and second clocked circuit means coupled to said first clocked circuit means and being responsive to said interstage signal and to a second clock pulse for selectively transferring said interstage signal according to said second clock pulse to provide an output signal corresponding to said interstage signal and a further fourth signal, said second clock pulse being in-phase with said first clock pulse, said second clocked circuit means including: a fourth CMOS clocked gate responsive to said interstage signal and being clocked by an inverted clock pulse corresponding to said second clock pulse and providing said output signal, a second CMOS nonclocked gate having an input terminal being coupled to said fourth CMOS clocked gate for transferring said output signal to provide said fourth signal, a fifth CMOS clocked gate being coupled to said second CMOS nonclocked gate and being responsive to said fourth signal and to said noninverted clock pulse for selectively transferring said fourth signal according to said noninverted clock pulse to provide a fifth signal which is fed back to the input terminal of said second CMOS nonclocked gate, whereby the combination of said first, second, third, fourth and fifth CMOS clocked gates and said first and second CMOS nonclocked gates constitute a racefree D-type flipflop.

Claim 8

A racefree CMOS clocked logic circuit comprising: first clocked circuit means including means for providing an input signal and being responsive to said input signal and to a first clock pulse, for selectively transferring said input signal according to said first clock pulse to provide an interstage signal corresponding to said input signal, said first clocked circuit means including: a first CMOS clocked gate responsive to said input signal and being clocked by an inverted clock pulse corresponding to said first clock pulse for providing said interstage signal, a second CMOS clocked gate being responsive to a first signal and a noninverted clocked pulse, said noninverted clock pulse being antiphasic to said inverted clock pulse for selectively transferring said first signal according to said noninverted clock pulse to provide a second signal, a first CMOS nonclocked logic gate having an input terminal coupled to said second CMOS clocked gate for transferring said second signal to provide said input signal, a third CMOS clocked gate coupled to said first CMOS nonclocked logic gate and being responsive to said input signal and to said inverted clock pulse for selectively transferring said input signal according to said inverted clock pulse to provide a third signal which is fed back to the input terminal of said first CMOS nonclocked logic gate; and second clocked circuit means coupled to said first clocked circuit means and being responsive to said interstage signal and to a second clock pulse for selectively transferring said interstage signal according to said second clock pulse to provide an output signal corresponding to said interstage signal and a further fourth signal, said second clock pulse being in-phase with said first clock pulse, said second clocked circuit means including: a fourth CMOS clocked gate responsive to said interstage signal and being clocked by an inverted clock pulse corresponding to said second clock pulse and providing said output signal, a second CMOS nonclocked gate having an input terminal being coupled to said fourth CMOS clocked gate for transferring said output signal to provide said fourth signal, a fifth CMOS clocked gate being coupled to said second CMOS nonclocked gate and being responsive to said fourth signal and to said noninverted clock pulse for selectively transferring said fourth signal according to said noninverted clock pulse to provide a fifth signal which is fed back to the input terminal of said second CMOS nonclocked gate, whereby the combination of said first, second, third, fourth and fifth CMOS clocked gates and said first and second CMOS nonclocked gates constitute a racefree D-type flipflop.

Claim 9

A racefree CMOS clocked logic circuit comprising: first clocked circuit means including means for providing an input signal and being responsive to said input signal and to a first clock pulse, for selectively transferring said input signal according to said first clock pulse to provide an interstage signal corresponding to said input signal, said first clocked circuit means including: a CMOS clocked NOR gate having a first input terminal responsive to said input signal and a second input terminal responsive to a first feedback signal, for providing said interstage signal according to the logical NOR of said input and first feedback signals, said CMOS clocked NOR gate being clocked by a clock pulse corresponding to said first clock pulse, a first CMOS clocked inverter responsive to a second feedback signal and an inverted clock pulse, said inverted clock pulse being antiphasic to said first clock pulse for selectively and phase-invertedly transferring said second feedback signal according to said inverted clock pulse to provide said input signal; and second clocked circuit means coupled to said first clocked circuit means and being responsive to said interstage signal and to a second clock pulse to provide an output signal corresponding to said interstage signal and said first and second feedback signals, said second clock pulse being in-phase with said first clock pulse, said second clocked circuit means including: a second CMOS clocked inverter coupled to said CMOS clocked NOR gate, for selectively transferring said interstage signal to provide said output signal, said second CMOS clocked inverter clocked by a clock pulse corresponding to said second clock pulse, a third CMOS clocked inverter responsive to said output signal and said inverted clock pulse, for selectively and phase-invertedly transferring said output signal according to said inverted clock pulse to provide said first feedback signal, a fourth CMOS clocked inverter responsive to said first feedback signal and said noninverted clock pulse, for selectively and phase-invertedly transferring said first feedback signal according to said noninverted clock pulse to provide said second feedback signal, whereby the combination of said first, second, third and fourth CMOS clocked inverters and said CMOS clocked NOR gate constitute a racefree frequency divider.

Claim 10

A racefree CMOS clocked logic circuit comprising: first clocked circuit means including means for providing an input signal and being responsive to said input signal and to a first clock pulse, for selectively transferring said input signal according to said first clock pulse to provide an interstage signal corresponding to said input signal, said first clocked circuit means including: a CMOS clocked NOR gate having a first input terminal responsive to said input signal and a second input terminal responsive to a first feedback signal, for providing said interstage signal according to the logical NOR of said input and first feedback signals, said CMOS clocked NOR gate being clocked by a clock pulse corresponding to said first clock pulse, a first CMOS clocked inverter responsive to a second feedback signal and an inverted clock pulse, said inverted clock pulse being antiphasic to said first clock pulse for selectively and phase-invertedly transferring said second feedback signal according to said inverted clock pulse to provide said input signal; and second clocked circuit means coupled to said first clocked circuit means and being responsive to said interstage signal and to a second clock pulse to provide an output signal corresponding to said interstage signal and said first and second feedback signals, said second clock pulse being in-phase with said first clock pulse, said second clocked circuit means including: a second CMOS clocked inverter coupled to said CMOS clocked NOR gate, for selectively transferring said interstage signal to provide said output signal, said second CMOS clocked inverter clocked by a clock pulse corresponding to said second clock pulse, a third CMOS clocked inverter responsive to said output signal and said inverted clock pulse, for selectively and phase-invertedly transferring said output signal according to said inverted clock pulse to provide said first feedback signal, a fourth CMOS clocked inverter responsive to said first feedback signal and said noninverted clock pulse, for selectively and phase-invertedly transferring said first feedback signal according to said noninverted clock pulse to provide said second feedback signal, whereby the combination of said first, second, third and fourth CMOS clocked inverters and said CMOS clocked NOR gate constitute a racefree frequency divider.