Phase comparator for biphase coded signal including preamble with code violation

Claim 3

A method according to claim 1, comprising generating the second signal with frequency dependent on said output signal.

Claim 4

A method according to claim 1, comprising creating a binary control signal in response to the second signal, the frequency of the binary control signal being equal to that of the second signal, and modifying the output signal according to the state of the binary control signal.

Claim 5

A method according to claim 1, wherein the output signal has at least two signal components and the method comprises creating a binary control signal in response to the second signal, the frequency of the binary control signal being equal to that of the second signal, and clearing at least one of said signal components according to the state of the binary control signal.

Claim 8

A phase comparison apparatus for comparing phase of a first periodic signal of a first frequency and a second periodic signal of a second frequency that closely matches the first frequency, said phase comparison apparatus comprising: a processing means for generating a periodic control signal in response to the second signal, wherein the frequency of the periodic control signal is equal to that of the second signal and the periodic control signal has a reset state and a non-reset state; and a phase comparator means connected to receive the first and second signals, a mask signal having an enable state and a disable state, and the control signal, and the phase comparator means being operative to produce an output signal according to the phase relationship between the first and second signals when the control signal is in its non-reset state and the mask signal is in the enable state and to modify the output signal to a predetermined state when the control signal enters its reset state.

Claim 9

A phase comparison apparatus for comparing phase of a first periodic signal of a first frequency and a second periodic signal of a second frequency that closely matches the first frequency, said phase comparison apparatus comprising: a processing means for generating a periodic control signal in response to the second signal, wherein the frequency of the periodic control signal is equal to that of the second signal and the periodic control signal has a reset state and a non-reset state; and a phase comparator means connected to receive the first and second signals, a mask signal having an enable state and a disable state, and the control signal, and the phase comparator means being operative to produce an output signal according to the phase relationship between the first and second signals when the control signal is in its non-reset state and the mask signal is in the enable state and to modify the output signal to a predetermined state when the control signal enters its reset state.

Claim 10

A phase comparison apparatus according to claim 6, wherein the phase comparator means also receives a mask signal having an enable state and a disable state, and wherein the phase comparator means is operative to produce said output signal only when the mask signal is in the enable state.

Claim 11

A phase comparison apparatus according to claim 6, wherein the phase comparator means receives a first clocking event from one of said first and second signals and a subsequent second clocking event from the other of said first and second signals and said output signal is representative of the time interval between the first clocking event and the second clocking event.

Claim 12

A phase comparison apparatus according to claim 6, wherein said phase comparator means produces a first output signal having an active state of a time duration representative of a positive phase difference between the first and second signals, and produces an opposite polarity, second output signal having an active state of a time duration representative of a negative phase difference between the first and second signals.

Claim 13

A phase comparison apparatus comprising: a phase comparator means for receiving a first periodic signal having a first frequency, a second periodic signal having a second frequency closely matching the first frequency, a control signal having a reset state and a non-reset state and a frequency equal to the second frequency, a clear signal having a logical true state and a logical false state, and a mask signal having an enable state and a disable state, and said phase comparator means being operative, if the mask signal is in the enable state, to produce a first output set signal upon receiving a first clocking event from one of said first and second signals, to produce a second output set signal of opposite polarity with respect to the first output set signal upon receiving a second clocking event from the other of said first and second signals, to clear the first and second output set signals in response to the clear signal being in the logical true state, and to clear at least one of said first and second output signals when the control signal is in the reset state; a coincidence means for receiving the first and second output set signal, and generating the clear signal in the logical true state in response to coincidence of the first and second output set signals and otherwise generating the clear signal in the logical false state; and a processing means for generating said second periodic signal and said control signal in response to said first and second output set signals.

Claim 14

A phase comparison apparatus comprising: a phase comparator means for receiving a first periodic signal having a first frequency, a second periodic signal having a second frequency closely matching the first frequency, a control signal having a reset state and a non-reset state and a frequency equal to the second frequency, a clear signal having a logical true state and a logical false state, and a mask signal having an enable state and a disable state, and said phase comparator means being operative, if the mask signal is in the enable state, to produce a first output set signal upon receiving a first clocking event from one of said first and second signals, to produce a second output set signal of opposite polarity with respect to the first output set signal upon receiving a second clocking event from the other of said first and second signals, to clear the first and second output set signals in response to the clear signal being in the logical true state, and to clear at least one of said first and second output signals when the control signal is in the reset state; a coincidence means for receiving the first and second output set signal, and generating the clear signal in the logical true state in response to coincidence of the first and second output set signals and otherwise generating the clear signal in the logical false state; and a processing means for generating said second periodic signal and said control signal in response to said first and second output set signals.

Claim 17

A method according to claim 11, comprising generating the second signal in response to the output signal, whereby the frequency of the second signal closely matches that of the extracted clock signal, generating a decoding signal in response to the output signal, and employing the decoding signal to decode the data signal and generate a preamble signal, and wherein step (d) comprises employing the preamble signal to disable step (b).

Claim 18

A method according to claim 11, wherein the output signal has at least two signal components and step (c) comprises clearing at least one of said signal components.

Claim 19

A method according to claim 13, wherein step (b) comprises generating a first output signal component if the extracted clock signal leads the second signal and generating a second output signal component if the extracted clock signal lags the second signal, and step (c) comprises generating a reset signal in a clear state at said predetermined phase during the cycle of the second signal and clearing at least one of the first and second output signal components in response to the reset signal being in said clear state.

Claim 20

A method according to claim 14, comprising generating the second signal in response to the first and second output signal components, whereby the frequency of the second signal closely matches that of the extracted clock signal, generating a decoding signal in response to the first and second output signal components, and employing the decoding signal to decode the data signal and generate a preamble signal, and wherein step (d) comprises employing the preamble signal to disable step (b).

Claim 21

A method according to claim 11, wherein step (b) comprises generating a first output signal component if the extracted clock signal leads the second signal and generating a second output signal component if the extracted clock signal lags the second signal, and step (c) comprises clearing at least one of the first and second output signal components.

Claim 22

A method according to claim 16, comprising generating the second signal in response to the first and second output signal components, whereby the frequency of the second signal closely matches that of the extracted clock signal, generating a decoding signal in response to the first and second output signal components, and employing the decoding signal to decode the data signal and generate a preamble signal, and wherein step (d) comprises employing the preamble signal to disable step (b).

Claim 23

A logic circuit comprising: a first D flip-flop having a D input, a clock input, a reset input, and an output, a second D flip-flop having a D input, a clock input, a reset input, and an output, an AND means having two inputs connected to the two outputs respectively of the first and second flip-flops and also having an output, the AND means asserting a logic 1 output in the event that the first and second flip-flops are both in a set state and otherwise asserting a logic 0 output, and an OR means having a first input connected to the output of the AND means, an output connected to the reset input of the first flip-flop, and also having a second input, whereby the first flip-flop is reset in the event that the two flip-flops are both in the set state or in the event that the OR means receives a logic 1 at its second input regardless of the whether the two flip-flops are both in the set state.

Claim 24

A logic circuit comprising: a first D flip-flop having a D input, a clock input, a reset input, and an output, a second D flip-flop having a D input, a clock input, a reset input, and an output, an AND means having two inputs connected to the two outputs respectively of the first and second flip-flops and also having an output, the AND means asserting a logic 1 output in the event that the first and second flip-flops are both in a set state and otherwise asserting a logic 0 output, and an OR means having a first input connected to the output of the AND means, an output connected to the reset input of the first flip-flop, and also having a second input, whereby the first flip-flop is reset in the event that the two flip-flops are both in the set state or in the event that the OR means receives a logic 1 at its second input regardless of the whether the two flip-flops are both in the set state.

Claim 25

A logic circuit according to claim 18, wherein the first and second flip-flops each have a Q output and the inputs of the AND means are connected to the Q outputs respectively and the output of the AND means is connected to the reset input of the second flip-flop, whereby the first and second flip-flops are reset in the event that the two flip-flops each have a logic 1 at the Q output and the first flip-flop is reset in the event that the OR means receives a logic 1 at its second input regardless of the Q outputs of the two flip-flops.