US4402084A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Regenerator having a code rule violation checking device
Assignee: Siemens AG
•
Filing: 1981-07-20
•
Granted: 1983-08-30
•
Expires: 2001-07-20
Abstract
Abstract For operational monitoring in PCM links, when a redundant code is used, the possibility is employed of establishing faults by violations of the code rule. In the recoding of the transmission signals in intermediate regenerators of the transmission link, it is necessary to provide a code rule violation checking device for each individual regenerator, which results in an increase in the expense in the regenerators. The code rule violation checking device disclosed is included in the pulse regenerator so that only one additional RS flip-flop, two time delay elements and two gate arrangements are necessary for this purpose. The invention may be employed in PCM links having transmission signals represented in the AMI code and, in particular, in transmission links employing element speeds of a few hundred Mbit/s.
Inventors
- 👤 Hans G. Jungmeister
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:57
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/20; H04L25/24; H04L25/242; H04L1/00; H04L1/24; H04L1/245; H04L1/247
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
242 words
A regenerator for PCM signals represented in the AMI code, comprising: input means for receiving positive and negative input pulses; first and second D flip-flops each including a D input, a Q output and a Q output; means connecting said input means to said D inputs of said first and second D flip-flops and operable to provide the positive input pulses to said first D flip-flop and negative input pulses to said second D flip-flops to cause said D flip-flops to produce respective pulses; an RS flip-flop including a Q output, a Q output and a set input and a reset input respectively connected to selected outputs of said D flip-flops and operable in response to pulses produced by said D flip-flops to regenerate the input signals supplied thereto via said first and second D flip-flops as respective unipolar pulse trains at said Q and Q outputs of said RS flip-flop, each unipolar pulse train containing the entire information received from the input pulses, the pulses of said pulse trains having a predetermined bit duration; and first and second gate circuits each including two inputs and an output, said outputs of said first and second gate circuits connected together as a wired OR gate for providing fault signals, a first input of each gate circuit connected to a respective output of said RS flip-flop and a second input of each gate circuit connected to a selected output of a respective D flip-flop.
Claim 2
Dependent Claim
242 words
A regenerator for PCM signals represented in the AMI code, comprising: input means for receiving positive and negative input pulses; first and second D flip-flops each including a D input, a Q output and a Q output; means connecting said input means to said D inputs of said first and second D flip-flops and operable to provide the positive input pulses to said first D flip-flop and negative input pulses to said second D flip-flops to cause said D flip-flops to produce respective pulses; an RS flip-flop including a Q output, a Q output and a set input and a reset input respectively connected to selected outputs of said D flip-flops and operable in response to pulses produced by said D flip-flops to regenerate the input signals supplied thereto via said first and second D flip-flops as respective unipolar pulse trains at said Q and Q outputs of said RS flip-flop, each unipolar pulse train containing the entire information received from the input pulses, the pulses of said pulse trains having a predetermined bit duration; and first and second gate circuits each including two inputs and an output, said outputs of said first and second gate circuits connected together as a wired OR gate for providing fault signals, a first input of each gate circuit connected to a respective output of said RS flip-flop and a second input of each gate circuit connected to a selected output of a respective D flip-flop.
Claim 3
Dependent Claim
53 words
The regenerator of claim 1, and further comprising: first and second time delay elements connected between respective outputs of said RS flip-flop and the respective inputs of said gate circuits, and effective to provide pulse transit times through said RS flip-flop and said delay elements corresponding to a total of one bit duration.
Claim 4
Dependent Claim
145 words
The regenerator of claim 2, wherein: said first and second gate circuits are NOR gates; said first input of said first NOR gate is connected to said Q output of said first D flip-flop; said first input of said second NOR gate is connected to the non-inverting output Q of said second D flip-flop; said reset input R of said RS flip-flop is connected to said non-inverting output Q of said first D flip-flop; said set input S of said RS flip-flop is connected to the inverting output Q of said second D flip-flop; said second input of said first NOR gate is connected via said first time delay element to the non-inverting output Q of said RS flip-flop; and said second input of said second NOR gate is connected via said second time delay element to the inverting output Q of said RS flip-flop.
Claim 5
Dependent Claim
111 words
The regenerator of claim 2, wherein: said first and second gates are AND gates; said first input of said first AND gate is connected to said reset input R of said RS flip-flop and said output Q of said first D flip-flop; said second input of said first AND gate is connected to said inverting output Q of said RS flip-flop; said first input of said second AND gate is connected to said set input S of said RS flip-flop and to said output Q of said second D flip-flop; and said second input of said second AND gate is connected to said the non-inverting output Q of said RS flip-flop.
Claim 6
Dependent Claim
105 words
The regenerator of claim 2, wherein: said input means comprises an input transformer including a center-tapped secondary winding having outer terminals and differential amplifiers connected to said outer terminals as amplitude decision devices, said amplitude decision devices connected to said D inputs of said D flip-flops; said non-inverting output Q of said first D flip-flop is connected to said reset input R of said RS flip-flop; said non-inverting output Q of said second D flip-flop is connected to said set input S of said RS flip-flop; and said inverting outputs Q of said two D flip-flops are respectively connected to inputs of said gate circuits.
Claim 7
Dependent Claim
13 words
The regenerator of claim 5, wherein said gate circuits are each NOR gates.
Claim 8
Dependent Claim
61 words
The regenerator of claim 2, wherein: said RS flip-flop comprises a time delay for the drop of the output level from the maximum to the minimum value which corresponds to the time delay for the rise of the output level from the minimum to the maximum value, and a signal transit time therethrough which is substantially shorter than one bit duration.
Claim 9
Dependent Claim
42 words
The regenerator of claim 1, and further comprising: a third D flip-flop having two non-inverting inputs linked by the logical OR-function, a non-inverting output and an inverting output, each of said inputs connected to one of the inputs of said RS flip-flop.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-08-29 | 1987-02-28 | 1987-08-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-08-29 | 1991-02-28 | 1991-08-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-08-29 | 1995-02-28 | 1995-08-30 | $7700.00 | Window Closed / Lapsed |