Apparatus for detecting the start of frame in bipolar transmission systems

Claim 2

Apparatus for detecting a code violation in an incoming bipolar information signal having different polarity pulses each of a given duration, comprising: clock means for providing an output clock signal of a frequency greater than the frequency of said bipolar signal, counting means responsive to said incoming bipolar signal to count a predetermined number of one polarity levels of said bipolar signal with respect to said clock means to provide an output signal when said one polarity level does not change to another polarity level subsequent to obtaining a count of said predetermined number, and means responsive to said output signal from said counting means and to said bipolar information signal to detect a violation in said signal whereby said violation is indicative of said one polarity level followed by another said one polarity level in succession.

Claim 3

The apparatus according to claim 1, wherein said bipolar signal is an AMI signal.

Claim 4

The apparatus according to claim 1, wherein said one polarity level is the positive level (P -- DATA) of said AMI signal.

Claim 5

The apparatus according to claim 1, wherein said one polarity level is the negative level (N -- DATA) of said AMI signal.

Claim 6

The apparatus according to claim 1, wherein said clock means provides a given number of pulses during each duration of said one polarity level of said AMI signal.

Claim 7

The apparatus according to claim 5, wherein the center of said polarity level is indicative of a predetermined number of said given number of pulses.

Claim 8

The apparatus according to claim 1, further including: logic means responsive to the detection of said violation in said signal to provide a start of frame signal.

Claim 9

The apparatus according to claim 7, wherein said logic means includes latch means responsive to said pulse to provide an enable signal during said pulse and operative to prime one input of said latch means to enable the next pulse to cause said means to provide said start of frame signal.

Claim 10

The apparatus according to claim 7, wherein said counter is a two stage ring counter including first and second JK flip-flops, with the clear inputs adapted to receive said one polarity level signal and with the clock inputs adapted to receive said output clock signal.

Claim 13

Apparatus for providing a start of frame (SOF) signal for an incoming bipolar information signal, wherein one binary state is alternately encoded with positive and negative polarity pulses, each pulse of a given duration and the other binary state is encoded with a zero or reference level and wherein a violation of said encoding occurs when the polarity level of said pulses remains the same for two or more successive pulses wherein said violation may constitute a start of frame (SOF) signal, comprising: means responsive to said bipolar signal to provide a first series of pulses indicative of said positive pulses and a second series of pulses indicative of said negative pulses, clock means operative to provide a high frequency clock output providing a predetermined number of pulses for each of said pulse durations, counting means responsive to said clock output and said first and second series of pulses to count to a predetermined number for each of said durations to provide a third series of pulses corresponding to true positive pulses and a fourth series of pulses corresponding to true negative pulses, by said counting means providing said third and fourth series of pulses relatively about the center of said pulse duration for each polarity, logic means responsive to said third and fourth series of pulses and said first and second series of pulses to provide an output signal (SOF) when at least two successive pulses indicative of said bipolar signal have the same polarity manifesting a code violation.

Claim 14

Apparatus for providing a start of frame (SOF) signal for an incoming bipolar information signal, wherein one binary state is alternately encoded with positive and negative polarity pulses, each pulse of a given duration and the other binary state is encoded with a zero or reference level and wherein a violation of said encoding occurs when the polarity level of said pulses remains the same for two or more successive pulses wherein said violation may constitute a start of frame (SOF) signal, comprising: means responsive to said bipolar signal to provide a first series of pulses indicative of said positive pulses and a second series of pulses indicative of said negative pulses, clock means operative to provide a high frequency clock output providing a predetermined number of pulses for each of said pulse durations, counting means responsive to said clock output and said first and second series of pulses to count to a predetermined number for each of said durations to provide a third series of pulses corresponding to true positive pulses and a fourth series of pulses corresponding to true negative pulses, by said counting means providing said third and fourth series of pulses relatively about the center of said pulse duration for each polarity, logic means responsive to said third and fourth series of pulses and said first and second series of pulses to provide an output signal (SOF) when at least two successive pulses indicative of said bipolar signal have the same polarity manifesting a code violation.

Claim 15

The apparatus according to claim 12, further including: combining means responsive to said first and second series of pulses to provide a fifth series of pulses wherein said fifth series of pulses is indicative of both said negative and positive levels.

Claim 16

The apparatus according to claim 13, wherein said clock means includes means responsive to said fifth series of pulses and a high frequency input signal to define each of said pulse durations in said fifth series of pulses by a given number of high frequency pulses to provide at an output a sixth pulse series from said fifth series with each pulse duration containing said given number of high frequency pulses.

Claim 17

The apparatus according to claim 14, wherein said counting means includes a first ring counter responsive to said first series of pulses and said sixth pulse series to count to a given count to provide at an output a first additional pulse if said positive level pulse remains positive for said duration after said count, whereby said additional pulse is nearer the center of said incoming pulse duration, a second ring counter responsive to said second series of pulses and said sixth pulse series to count to said given count to provide at an output a second additional pulse if said negative level pulse remains negative for said duration after said count, whereby said second additional pulse is nearer the center of said incoming pulse duration.

Claim 18

The apparatus according to claim 15, wherein said first and second counters are two stage counters employing JK flip-flops.

Claim 19

The apparatus according to claim 16, wherein said logic means includes first and second latches with said first latch responsive to said first additional pulse to enable the same and with said second latch responsive to said second additional pulse to enable the same, with said first latch further responsive to said first series of pulses to cause said first latch to provide an output after enabled, for two successive pulses of said bipolar signal of a positive polarity and with said second latch further responsive to said second series of pulses to cause said second latch to provide an output, after enabled, for two successive pulses of said bipolar signal of a negative polarity, with said output of said first or second latch indicative of said start of frame (SOF) signal.

Claim 20

The apparatus according to claim 17, including: first reset means responsive to said first additional pulse and coupled to said second latch for resetting said second latch when said first additional pulse is provided, second reset means responsive to said second additional pulse and coupled to said first latch for resetting said first latch when said second additional pulse is provided.

Claim 21

The apparatus according to claim 18, wherein said bipolar signal is an AMI signal.

Claim 22

Apparatus for providing a start of frame (SOF) signal for an incoming bipolar information signal wherein one binary state is alternately encoded with positive and negative polarity pulses each of a given duration and the other binary state is encoded with a zero or reference level and wherein a violation of said encoding occurs when the polarity level of said pulses remains the same for two or more successive pulses indicating a code violation which violation can be used as a start of frame (SOF) signal, comprising: means responsive to said incoming bipolar signal to provide therefrom a first signal (P -- DATA) indicative of positive polarity data of said bipolar signal, a second signal (N -- DATA) indicative of negative polarity data of said bipolar signal, and a third signal (R -- DATA) indicative of both negative and positive polarity data, with each of said signals having pulses of the same duration, clock means responsive to said third signal for providing at an output a clock signal having a predetermined number of pulses for each pulse duration of said first, second and third signals, first counting means responsive to said clock signal and said first signal to count to a predetermined number during each pulse duration of said first signal according to said clock signal until said predetermined number is reached and to provide a first output pulse if said polarity of said first signal did not change after said number is reached, second counting means responsive to said clock signal and said second signal to count to said predetermined number during each pulse duration of said second signal according to said clock signal until said predetermined number is reached and to provide a second output pulse if said polarity of said second signal did not change after said number is reached, output logic means responsive to said first, second and third signals including first and second latches with said first latch enabled by said first output pulse and with said second latch enabled by said second output pulse, with said first latch operative to provide an output signal when said input bipolar signal exhibits a positive polarity for two successive pulses, and with said second latch operative to provide an output signal when said input bipolar signal exhibits a negative polarity for two successive pulses, with said output signals combined so that either signal indicates a code violation which can be employed as a start of frame (SOF) signal.

Claim 23

Apparatus for providing a start of frame (SOF) signal for an incoming bipolar information signal wherein one binary state is alternately encoded with positive and negative polarity pulses each of a given duration and the other binary state is encoded with a zero or reference level and wherein a violation of said encoding occurs when the polarity level of said pulses remains the same for two or more successive pulses indicating a code violation which violation can be used as a start of frame (SOF) signal, comprising: means responsive to said incoming bipolar signal to provide therefrom a first signal (P -- DATA) indicative of positive polarity data of said bipolar signal, a second signal (N -- DATA) indicative of negative polarity data of said bipolar signal, and a third signal (R -- DATA) indicative of both negative and positive polarity data, with each of said signals having pulses of the same duration, clock means responsive to said third signal for providing at an output a clock signal having a predetermined number of pulses for each pulse duration of said first, second and third signals, first counting means responsive to said clock signal and said first signal to count to a predetermined number during each pulse duration of said first signal according to said clock signal until said predetermined number is reached and to provide a first output pulse if said polarity of said first signal did not change after said number is reached, second counting means responsive to said clock signal and said second signal to count to said predetermined number during each pulse duration of said second signal according to said clock signal until said predetermined number is reached and to provide a second output pulse if said polarity of said second signal did not change after said number is reached, output logic means responsive to said first, second and third signals including first and second latches with said first latch enabled by said first output pulse and with said second latch enabled by said second output pulse, with said first latch operative to provide an output signal when said input bipolar signal exhibits a positive polarity for two successive pulses, and with said second latch operative to provide an output signal when said input bipolar signal exhibits a negative polarity for two successive pulses, with said output signals combined so that either signal indicates a code violation which can be employed as a start of frame (SOF) signal.