Stacked capacitor type semiconductor memory device and manufacturing method thereof

Claim 2

A capacitor of a semiconductor memory device, comprising: a semiconductor substrate having a conductive region on a major surface thereof, an insulating layer formed on the major surface of said semiconductor substrate, a gate electrode being formed above said major surface of said semiconductor substrate through a portion of said insulating layer, a first electrode layer formed extending on a major surface of said insulating layer and on said conductive region, a dielectric layer covering a surface of said first electrode layer, and a second electrode layer formed on a surface of said dielectric layer, wherein, viewed in vertical cross-section, said first electrode layer comprises two projections of uniform thickness throughout elongated in a direction substantially normal to said major surface of said substrate, at least one said projection being located above and overlapping a portion of said gate electrode, said projections having inner walls facing each other on opposite sides of a central region and further having outer walls, and further wherein said dielectric layer and said second electrode layer are formed continuously on said inner walls and outer walls to enclose said projections.

Claim 3

A capacitor of a semiconductor memory device in accordance with claim 1, wherein upper ends of said first electrode layer lie in a common plane parallel to said substrate.

Claim 4

A memory cell of a semiconductor memory device having one transistor and one storage means, comprising: a semiconductor substrate having a flat major surface; a pair of source/drain regions of said transistor formed in the major surface of said semiconductor substrate; a gate electrode of said transistor formed between said pair of source/drain regions in the major surface of said semiconductor substrate, with a gate insulator therebetween; one electrode of said storage means having a first portion electrically connected to the one source/drain region of said transistor, a second portion electrically insulated from said gate electrode and formed to be extending continuously from said first portion over said gate electrode, a third portion formed to be extending continuously from said second portion onto an isolation region formed in the major surface of said semiconductor substrate for isolating between memory cells, a fourth portion formed to be continuously projecting upward from said second portion, overlapping said gate electrode, and having a pair of substantially parallel side surfaces and a top surface, and a fifth portion formed to be continuously projecting upwardly from, and overlapping, said third portion and having a pair of substantially parallel side surfaces and a top surface, inner side surfaces of said fourth and fifth portions facing each other; and the other electrode of said storage means formed to be opposing to said one electrode with a dielectric layer therebetween and formed continuously on (1) a surface of said first portion, (2) a surface of said second portion, (3) a surface of said third portion, (4) the pair of side surfaces and the top surface of said fourth portion and the pair of side surfaces and the top surface of said fifth portion included in said one electrode of said storage means.

Claim 5

A memory cell of a semiconductor memory device having one transistor and one storage means, comprising: a semiconductor substrate having a flat major surface; a pair of source/drain regions of said transistor formed in the major surface of said semiconductor substrate; a gate electrode of said transistor formed between said pair of source/drain regions in the major surface of said semiconductor substrate, with a gate insulator therebetween; one electrode of said storage means having a first portion electrically connected to the one source/drain region of said transistor, a second portion electrically insulated from said gate electrode and formed to be extending continuously from said first portion over said gate electrode, a third portion formed to be extending continuously from said second portion onto an isolation region formed in the major surface of said semiconductor substrate for isolating between memory cells, a fourth portion formed to be continuously projecting upward from said second portion, overlapping said gate electrode, and having a pair of substantially parallel side surfaces and a top surface, and a fifth portion formed to be continuously projecting upwardly from, and overlapping, said third portion and having a pair of substantially parallel side surfaces and a top surface, inner side surfaces of said fourth and fifth portions facing each other; and the other electrode of said storage means formed to be opposing to said one electrode with a dielectric layer therebetween and formed continuously on (1) a surface of said first portion, (2) a surface of said second portion, (3) a surface of said third portion, (4) the pair of side surfaces and the top surface of said fourth portion and the pair of side surfaces and the top surface of said fifth portion included in said one electrode of said storage means.

Claim 6

The memory cell according to claim 3, wherein: said second and third portions of said storage means are continuously formed to surround said first portion, and said fourth and fifth portions are also continuously formed to surround said first portion.

Claim 7

The device of claim 4, wherein a gate electrode of said memory device is formed above the major surface of said substrate through a portion of said insulating layer, and wherein at least part of said projecting portions of said first electrode layer is formed above and overlapping said gate electrode.