Patent US5457433A successfully refreshed from Google Patents.
US5457433A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low-power inverter for crystal oscillator buffer or the like
Assignee: Motorola Solutions Inc
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Filing: 1993-08-25
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Granted: 1995-10-10
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Expires: 2013-08-25
Abstract
Abstract A low-power inverter (53) reduces power consumption over known inverter designs and is especially well-adapted for serving as a buffer in a Pierce crystal oscillator with a large load capacitance. The inverter (53) includes P- and N-side source-follower stages (310, 320) driving CMOS output transistor pairs (350, 360). The source followers are current-limited through current sources (311, 313, 321, 323) which are biased by a stable reference voltage such as a bandgap reference voltage. Clamping devices (331, 332) are provided to limit the voltages on the gates of the output transistors (350, 360), thereby limiting maximum currents thereof. In addition, a helper device (332) is connected to the gate of a P-channel output transistor (350). The P-channel output transistor (350) typically has a large gate area and thus a large capacitance, and the helper device (332) quickly increases the voltage at the gate when an input signal changes to a high voltage.
Inventors
- 👤 Alan L. Westwick
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:37
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/03; H03K3/0307; H03B; H03B5/00; H03B5/30; H03B5/32; H03B5/36; H03B5/366; H03K19/00; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/0948; H03B2202/00; H03B2202/04; H03B2202/042
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
282 words
A low-power inverter for a circuit such as a crystal oscillator buffer, comprising: an input node for receiving an input signal; an output node for providing an output signal; a first P-channel transistor having a source coupled to a first power supply voltage terminal, a gate coupled to said input node, and a drain coupled to said output node for providing said output signal; a first N-channel transistor having a drain coupled to said output node, a gate, and a source coupled to a second power supply voltage terminal; a first source follower stage having an input terminal coupled to said input node, and an output terminal coupled to said gate of said first N-channel transistor, said first source follower stage comprising: a first current source having a first terminal coupled to said first power supply voltage terminal, and a second terminal, for conducting a first predetermined current; a second N-channel transistor having a drain coupled to said second terminal of said first current source, a gate coupled to said input node, and a source coupled to said gate of said first N-channel transistor; and a second current source having a first terminal coupled to said source of said second N-channel transistor, and a second terminal coupled to said second power supply voltage terminal, for conducting a second predetermined current; and first clamp means coupled to said gate of said first N-channel transistor and to said second power supply voltage terminal, for clamping a voltage at said gate of said first N-channel transistor to be less than, a first predetermined voltage greater than a voltage of said second power supply voltage terminal, thereby limiting a drain-to-source current of said first N-channel transistor.
Claim 2
Dependent Claim
282 words
A low-power inverter for a circuit such as a crystal oscillator buffer, comprising: an input node for receiving an input signal; an output node for providing an output signal; a first P-channel transistor having a source coupled to a first power supply voltage terminal, a gate coupled to said input node, and a drain coupled to said output node for providing said output signal; a first N-channel transistor having a drain coupled to said output node, a gate, and a source coupled to a second power supply voltage terminal; a first source follower stage having an input terminal coupled to said input node, and an output terminal coupled to said gate of said first N-channel transistor, said first source follower stage comprising: a first current source having a first terminal coupled to said first power supply voltage terminal, and a second terminal, for conducting a first predetermined current; a second N-channel transistor having a drain coupled to said second terminal of said first current source, a gate coupled to said input node, and a source coupled to said gate of said first N-channel transistor; and a second current source having a first terminal coupled to said source of said second N-channel transistor, and a second terminal coupled to said second power supply voltage terminal, for conducting a second predetermined current; and first clamp means coupled to said gate of said first N-channel transistor and to said second power supply voltage terminal, for clamping a voltage at said gate of said first N-channel transistor to be less than, a first predetermined voltage greater than a voltage of said second power supply voltage terminal, thereby limiting a drain-to-source current of said first N-channel transistor.
Claim 3
Dependent Claim
47 words
The low-power inverter of claim 1 further comprising a second P-channel transistor having a source coupled to said first power supply voltage terminal, a gate coupled to said second terminal of said second current source, and a drain coupled to said gate of said first P-channel transistor.
Claim 4
Dependent Claim
50 words
The low-power inverter of claim 1 wherein said first clamp means comprises a third N-channel transistor having a drain coupled to said gate of said first N-channel transistor, a gate coupled to said gate of said first N-channel transistor, and a source coupled to said second power supply voltage terminal.
Claim 5
Dependent Claim
97 words
The low-power inverter of claim 1 further comprising: a second source follower stage having an input terminal coupled to said input node, and an output terminal coupled to said gate of said first P-channel transistor; and second clamp means coupled to said gate of said first P-channel transistor and to said first power supply voltage terminal, for clamping a voltage at said gate of said first P-channel transistor to be greater than, a second predetermined voltage less than a voltage of said first power supply voltage terminal, thereby limiting a drain-to-source current of said first P-channel transistor.
Claim 6
Dependent Claim
93 words
The low-power inverter of claim 4 wherein said second source follower stage comprises: a first current source having a first terminal coupled to said first power supply voltage terminal, and a second terminal coupled to said gate of said first P-channel transistor, for conducting a first predetermined current; and a second P-channel transistor having a source coupled to said second terminal of said first current source and to said gate of said first P-channel transistor, a gate coupled to said input node, and a drain coupled to said second power supply voltage terminal.
Claim 7
Dependent Claim
49 words
The low-power inverter of claim 5 wherein said second source follower stage further comprises a second current source having a first terminal coupled to said drain of said second P-channel transistor, and a second terminal coupled to said second power supply voltage terminal, for conducting a second predetermined current.
Claim 8
Dependent Claim
50 words
The low-power inverter of claim 4 wherein said second clamp means comprises a third P-channel transistor having a source coupled to said first power supply voltage terminal, a gate coupled to said gate of said first P-channel transistor, and a drain coupled to said gate of said first P-channel transistor.
Claim 9
Dependent Claim
292 words
A low-power inverter for a circuit such as a crystal oscillator buffer, comprising: an input node for receiving an input signal; an output node for providing an output signal; a first P-channel transistor having a source coupled to a first power supply voltage terminal, a gate, and a drain coupled to said output node for providing said output signal; a first N-channel transistor having a drain coupled to said output node, a gate coupled to said input node, and a source coupled to a second power supply voltage terminal; a source follower stage having an input terminal coupled to said input node, and an output terminal coupled to said gate of said first P-channel transistor, said source follower stage comprising: a first current source having a first terminal coupled to said first power supply voltage terminal, and a second terminal coupled to said gate of said first P-channel transistor, for conducting a first predetermined current; a second P-channel transistor having a source coupled to said second terminal of said first current source and to said gate of said first P-channel transistor, a gate coupled to said input node for receiving said input signal, and a drain; and a second current source having a first terminal coupled to said drain of said second P-channel transistor, and a second terminal coupled to said second power supply voltage terminal, for conducting a second predetermined current, and clamp means coupled to said first power supply voltage terminal and to said gate of said first P-channel transistor, for clamping a voltage at said gate of said first P-channel transistor to be greater than, a predetermined voltage less than a voltage of said first power supply voltage terminal, thereby limiting a drain-to-source current of said first P-channel transistor.
Claim 10
Dependent Claim
292 words
A low-power inverter for a circuit such as a crystal oscillator buffer, comprising: an input node for receiving an input signal; an output node for providing an output signal; a first P-channel transistor having a source coupled to a first power supply voltage terminal, a gate, and a drain coupled to said output node for providing said output signal; a first N-channel transistor having a drain coupled to said output node, a gate coupled to said input node, and a source coupled to a second power supply voltage terminal; a source follower stage having an input terminal coupled to said input node, and an output terminal coupled to said gate of said first P-channel transistor, said source follower stage comprising: a first current source having a first terminal coupled to said first power supply voltage terminal, and a second terminal coupled to said gate of said first P-channel transistor, for conducting a first predetermined current; a second P-channel transistor having a source coupled to said second terminal of said first current source and to said gate of said first P-channel transistor, a gate coupled to said input node for receiving said input signal, and a drain; and a second current source having a first terminal coupled to said drain of said second P-channel transistor, and a second terminal coupled to said second power supply voltage terminal, for conducting a second predetermined current, and clamp means coupled to said first power supply voltage terminal and to said gate of said first P-channel transistor, for clamping a voltage at said gate of said first P-channel transistor to be greater than, a predetermined voltage less than a voltage of said first power supply voltage terminal, thereby limiting a drain-to-source current of said first P-channel transistor.
Claim 11
Dependent Claim
49 words
The low-power inverter of claim 8 wherein said clamp means comprises a third P-channel transistor having a source coupled to said first power supply voltage terminal, a gate coupled to said gate of said first P-channel transistor, and a drain coupled to said gate of said first P-channel transistor.
Claim 12
Dependent Claim
346 words
A low-power inverter for a circuit such as a crystal oscillator buffer, comprising: an input node for receiving an input signal; an output node for providing an output signal; a first P-channel transistor having a source coupled to a first power supply voltage terminal, a gate, and a drain coupled to said output node for providing said output signal; a first N-channel transistor having a drain coupled to said output node, a gate, and a source coupled to a second power supply voltage terminal; a first current source having a first terminal coupled to said first power supply voltage terminal, and a second terminal, for conducting a first predetermined current; a second N-channel transistor having a drain coupled to said second terminal of said first current source, a gate coupled to said input node, and a source coupled to said gate of said first N-channel transistor; a second current source having a first terminal coupled to said gate of said first N-channel transistor and to said source of said second N-channel transistor, and a second terminal coupled to said second power supply voltage terminal, for conducting a second predetermined current; a third N-channel transistor having a drain coupled to said gate of said first N-channel transistor, a gate coupled to said gate of said first N-channel transistor, and a source coupled to said second power supply voltage terminal; a third current source having a first terminal coupled to said first power supply voltage terminal, and a second terminal coupled to said gate of said first P-channel transistor, for conducting a third predetermined current; a second P-channel transistor having a source coupled to said second terminal of said second current source and to said gate of said first P-channel transistor, a gate coupled to said input node, and a drain coupled to said second power supply voltage terminal; and a third P-channel transistor having a source coupled to said first power supply voltage terminal, a gate coupled to said gate of said first P-channel transistor, and a drain coupled to said gate of said first P-channel transistor.
Claim 13
Dependent Claim
346 words
A low-power inverter for a circuit such as a crystal oscillator buffer, comprising: an input node for receiving an input signal; an output node for providing an output signal; a first P-channel transistor having a source coupled to a first power supply voltage terminal, a gate, and a drain coupled to said output node for providing said output signal; a first N-channel transistor having a drain coupled to said output node, a gate, and a source coupled to a second power supply voltage terminal; a first current source having a first terminal coupled to said first power supply voltage terminal, and a second terminal, for conducting a first predetermined current; a second N-channel transistor having a drain coupled to said second terminal of said first current source, a gate coupled to said input node, and a source coupled to said gate of said first N-channel transistor; a second current source having a first terminal coupled to said gate of said first N-channel transistor and to said source of said second N-channel transistor, and a second terminal coupled to said second power supply voltage terminal, for conducting a second predetermined current; a third N-channel transistor having a drain coupled to said gate of said first N-channel transistor, a gate coupled to said gate of said first N-channel transistor, and a source coupled to said second power supply voltage terminal; a third current source having a first terminal coupled to said first power supply voltage terminal, and a second terminal coupled to said gate of said first P-channel transistor, for conducting a third predetermined current; a second P-channel transistor having a source coupled to said second terminal of said second current source and to said gate of said first P-channel transistor, a gate coupled to said input node, and a drain coupled to said second power supply voltage terminal; and a third P-channel transistor having a source coupled to said first power supply voltage terminal, a gate coupled to said gate of said first P-channel transistor, and a drain coupled to said gate of said first P-channel transistor.
Claim 14
Dependent Claim
47 words
The low-power inverter of claim 10 further comprising a fourth P-channel transistor having a source coupled to said first power supply voltage terminal, a gate coupled to said second terminal of said first current source, and a drain coupled to said gate of said first P-channel transistor.
Claim 15
Dependent Claim
43 words
The low-power inverter of claim 10 further comprising a third current source having a first terminal coupled to said drain of said second P-channel transistor, and a second terminal coupled to said second power supply voltage terminal, for conducting a fourth predetermined current.
Claim 16
Dependent Claim
376 words
An oscillator comprising: a first node for being coupled to a first terminal of a crystal; a second node for being coupled to a second terminal of a crystal; first and second power supply voltage terminals; a first P-channel transistor having a source coupled to said first power supply voltage terminal, a gate, and a drain coupled to said second node; a first N-channel transistor having a drain coupled to said second node, a gate, and a source coupled to said second power supply voltage terminal; a first source follower stage having an input terminal coupled to said first node, and an output terminal coupled to said gate of said first N-channel transistor, said first source follower stage comprising; a first current source having a first terminal coupled to said first power supply voltage terminal, and a second terminal, for conducting a first predetermined current; a second N-channel transistor having a drain coupled to said second terminal of said first current source, a gate coupled to said first node, and a source coupled to said gate of said first N-channel transistor; and a second current source having a first terminal coupled to said gate of said first N-channel transistor and to said source of said second N-channel transistor, and a second terminal coupled to said second power supply voltage terminal, for conducting a second predetermined current; first clamp means coupled to said gate of said first N-channel transistor and to said second power supply voltage terminal, for clamping a voltage at said gate of said first N-channel transistor to be less than, a first predetermined voltage greater than a voltage of said second power supply voltage terminal, thereby limiting a drain-to-source current of said first N-channel transistor; a second source follower stage having an input terminal coupled to said first node, and an output terminal coupled to said gate of said first P-channel transistor; and second clamp means coupled to said gate of said first P-channel transistor and to said first power supply voltage terminal, for clamping a voltage at said gate of said first P-channel transistor to be greater than, a second predetermined voltage less than a voltage of said first power supply voltage terminal, thereby limiting a drain-to-source current of said first P-channel transistor.
Claim 17
Dependent Claim
376 words
An oscillator comprising: a first node for being coupled to a first terminal of a crystal; a second node for being coupled to a second terminal of a crystal; first and second power supply voltage terminals; a first P-channel transistor having a source coupled to said first power supply voltage terminal, a gate, and a drain coupled to said second node; a first N-channel transistor having a drain coupled to said second node, a gate, and a source coupled to said second power supply voltage terminal; a first source follower stage having an input terminal coupled to said first node, and an output terminal coupled to said gate of said first N-channel transistor, said first source follower stage comprising; a first current source having a first terminal coupled to said first power supply voltage terminal, and a second terminal, for conducting a first predetermined current; a second N-channel transistor having a drain coupled to said second terminal of said first current source, a gate coupled to said first node, and a source coupled to said gate of said first N-channel transistor; and a second current source having a first terminal coupled to said gate of said first N-channel transistor and to said source of said second N-channel transistor, and a second terminal coupled to said second power supply voltage terminal, for conducting a second predetermined current; first clamp means coupled to said gate of said first N-channel transistor and to said second power supply voltage terminal, for clamping a voltage at said gate of said first N-channel transistor to be less than, a first predetermined voltage greater than a voltage of said second power supply voltage terminal, thereby limiting a drain-to-source current of said first N-channel transistor; a second source follower stage having an input terminal coupled to said first node, and an output terminal coupled to said gate of said first P-channel transistor; and second clamp means coupled to said gate of said first P-channel transistor and to said first power supply voltage terminal, for clamping a voltage at said gate of said first P-channel transistor to be greater than, a second predetermined voltage less than a voltage of said first power supply voltage terminal, thereby limiting a drain-to-source current of said first P-channel transistor.
Claim 18
Dependent Claim
46 words
The oscillator of claim 13 further comprising a second P-channel transistor having a source coupled to said first power supply voltage terminal, a gate coupled to said second terminal of said first current source, and a drain coupled to said gate of said first P-channel transistor.
Claim 19
Dependent Claim
49 words
The oscillator of claim 13 wherein said first clamp means comprises a third N-channel transistor having a drain coupled to said gate of said first N-channel transistor, a gate coupled to said gate of said first N-channel transistor, and a source coupled to said second power supply voltage terminal.
Claim 20
Dependent Claim
49 words
The oscillator of claim 13 wherein said second clamp means comprises a third P-channel transistor having a source coupled to said first power supply voltage terminal, a gate coupled to said gate of said first P-channel transistor, and a drain coupled to said gate of said first P-channel transistor.
Claim 21
Dependent Claim
76 words
The oscillator of claim 13 further comprising: a resistor having a first terminal coupled to said first node, and a second terminal coupled to said second node; a first capacitor having a first terminal coupled to said first node, and a second terminal coupled to said second power supply voltage terminal; and a second capacitor having a first terminal coupled to said second node, and a second terminal coupled to said second power supply voltage terminal.
Claim 22
Dependent Claim
259 words
A low-power inverter for a circuit such as a crystal oscillator buffer, comprising: an input node for receiving an input signal; an output node for providing an output signal; a first MOS transistor of a first conductivity type having a first current electrode coupled to a first power supply voltage terminal, a gate coupled to said input node, and a second current electrode coupled to said output node for providing said output signal; a second MOS transistor of a second conductivity type having a first current electrode coupled to said output node, a gate, and a second current electrode coupled to a second power supply voltage terminal; a first source follower stage having an input terminal coupled to said input node, and an output terminal coupled to said gate of said second MOS transistor, comprising: a first current source having a first terminal coupled to said first power supply voltage terminal, and a second terminal, for conducting a first predetermined current; and a third MOS transistor of said second conductivity type having a first current electrode coupled to said second terminal of said first current source, a gate coupled to said input node, and a second current electrode coupled to said gate of said second MOS transistor; and a fourth MOS transistor of said second conductivity type having a first current electrode coupled to said second current electrode of said third MOS transistor, a gate coupled to said second current electrode of said third MOS transistor, and a second current electrode coupled to said second power supply voltage terminal.
Claim 23
Dependent Claim
259 words
A low-power inverter for a circuit such as a crystal oscillator buffer, comprising: an input node for receiving an input signal; an output node for providing an output signal; a first MOS transistor of a first conductivity type having a first current electrode coupled to a first power supply voltage terminal, a gate coupled to said input node, and a second current electrode coupled to said output node for providing said output signal; a second MOS transistor of a second conductivity type having a first current electrode coupled to said output node, a gate, and a second current electrode coupled to a second power supply voltage terminal; a first source follower stage having an input terminal coupled to said input node, and an output terminal coupled to said gate of said second MOS transistor, comprising: a first current source having a first terminal coupled to said first power supply voltage terminal, and a second terminal, for conducting a first predetermined current; and a third MOS transistor of said second conductivity type having a first current electrode coupled to said second terminal of said first current source, a gate coupled to said input node, and a second current electrode coupled to said gate of said second MOS transistor; and a fourth MOS transistor of said second conductivity type having a first current electrode coupled to said second current electrode of said third MOS transistor, a gate coupled to said second current electrode of said third MOS transistor, and a second current electrode coupled to said second power supply voltage terminal.
Claim 24
Dependent Claim
51 words
The low-power inverter of claim 18 wherein said first source follower stage further comprises a second current source having a first terminal coupled to said second current electrode of said third MOS transistor, and a second terminal coupled to said second power supply voltage terminal, for conducting a second predetermined current.
Claim 25
Dependent Claim
149 words
The low-power inverter of claim 18 further comprising a second source follower stage having an input terminal coupled to said input node, and an output terminal coupled to said gate of said first MOS transistor, comprising: a fifth MOS transistor of said first conductivity type having a first current electrode coupled to said gate of said first MOS transistor, a gate coupled to said input node, and a second current electrode; a third current source having a first terminal coupled to said second current electrode of said fifth MOS transistor, and a second terminal coupled to said second power supply voltage terminal; and a sixth MOS transistor having a first current electrode coupled to said first power supply voltage terminal, a gate coupled to said first current electrode of said fifth MOS transistor, and a second current electrode coupled to said first current electrode of said fifth MOS transistor.
Claim 26
Dependent Claim
20 words
The low-power inverter of claim 18 wherein said first conductivity type is P-channel and said second conductivity type is N-channel.
Claim 27
Dependent Claim
20 words
The low-power inverter of claim 18 wherein said first conductivity type is N-channel and said second conductivity type is P-channel.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-10-09 | 1999-04-10 | 1999-10-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-10-09 | 2003-04-10 | 2003-10-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-10-09 | 2007-04-10 | 2007-10-10 | $7700.00 | Window Closed / Lapsed |