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US5065049A Expired / Lapsed US ⏱️ 0.0 years remaining

MOS driver circuit having clamp means to hold the output voltage constant regardless of variations in the operating voltage

Assignee: Samsung Electronics Co Ltd
•
Filing: 1990-12-04
•
Granted: 1991-11-12
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Expires: 2010-12-04
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Abstract

Abstract A MOS driver circuit comprises a pull-up NMOS transistor, a pull-down NMOS transistor, and a clamper circuit. The pull-up NMOS transistor has a source connected to an output terminal and a gate connected to a boosting node supplied with a boosted voltage when the output terminal is driven to a "high" state. The pull-down NMOS transistor has a drain connected to the output terminal and a source connected to the ground voltage, and is turned on when the output terminal is driven to a "low" state. The clamper circuit clamps the boosted voltage to a predetermined voltage by opening a current path from the boosting node to the output node when the boosted voltage supplied to the boosting node is greater than the predetermined voltage. In the circuit, the noise in the power and ground lines, which is generated due to the variation of the output voltage caused by the variation of the supply voltage, is prevented. Also, since the clamper circuit of the present invention discharges the charge of the boosting node to the output terminal, more charge can be discharged within short time during the transition from a low output state to a high state, thereby resulting in a more effective clamping operation.

Inventors

  • 👤 Hyeon-Sun Jang

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 15:59
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/06; H03K17/063; H03K17/14; H03K17/145; H03K5/00; H03K5/01; H03K5/08

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 121 words
A MOS driver circuit comprising: a pull-up NMOS transistor having a drain connected to a supply voltage, a source connected to an output terminal and a gate connected to a boosting node supplied with a boosted voltage when said output terminal is driven to a "high" state; a pull-down NMOS transistor having a drain connected to said output terminal and a source connected to a ground voltage, and being turned on when said output terminal is driven to a "low" state; and clamper means for clamping said boosted voltage to a predetermined voltage by opening a current path connecting said boosting node to said output node when said boosted voltage supplied to said boosting node is greater than the predetermined voltage.
Claim 2
Dependent Claim 121 words
A MOS driver circuit comprising: a pull-up NMOS transistor having a drain connected to a supply voltage, a source connected to an output terminal and a gate connected to a boosting node supplied with a boosted voltage when said output terminal is driven to a "high" state; a pull-down NMOS transistor having a drain connected to said output terminal and a source connected to a ground voltage, and being turned on when said output terminal is driven to a "low" state; and clamper means for clamping said boosted voltage to a predetermined voltage by opening a current path connecting said boosting node to said output node when said boosted voltage supplied to said boosting node is greater than the predetermined voltage.
Claim 3
Dependent Claim 71 words
A MOS driver circuit of claim 1, wherein said clamper means comprises: generating means for generating a constant reference voltage regardless of a variation of said supply voltage; and switch means, connected between said boosting node and said output node which is turned on when the boosted voltage supplied to said boosting node is greater than the summation of the reference voltage of said generating means and a threshold voltage thereof.
Claim 4
Dependent Claim 111 words
The MOS driver circuit of claim 2, wherein said generating means comprises: a PMOS transistor connected between said supply voltage and a reference voltage output terminal and turned on in response to an enable signal; n diodes connected to one another in forward direction between said reference voltage output terminal and said ground voltage, for providing said reference voltage; and an NMOS transistor having a source to drain path connected between said reference voltage output terminal and said n diodes and a gate coupled to said supply voltage, said NMOS transistor being turned on when a difference between the supply voltage and the reference voltage is larger than a threshold voltage.
Claim 5
Dependent Claim 66 words
The MOS driver circuit of claim 2, wherein said switch means comprises: a first PMOS transistor having a source connected to said boosting node, a gate connected to said reference voltage and a drain; and a second PMOS transistor having a source connected to the drain of said first PMOS transistor, a drain connected to said output node, and a gate connected to said reference voltage.
Claim 6
Dependent Claim 37 words
The MOS driver circuit of claim 1, wherein the predetermined voltage of said clamper means is set to a summation of a normal supply voltage and a threshold voltages of at least one of said MOS transistors.

References Cited (Backward Citations)

US4678944A Cited
US4866308A Cited
US4972104A Cited
US4998029A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1994-11-11 1995-05-13 1995-11-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1998-11-11 1999-05-13 1999-11-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2002-11-11 2003-05-13 2003-11-12 $7700.00 Window Closed / Lapsed

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