US5216293A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS output buffer with pre-drive circuitry to control slew rate of main drive transistors
Assignee: Toshiba Corp
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Filing: 1991-12-30
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Granted: 1993-06-01
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Expires: 2011-12-30
Abstract
Abstract A CMOS output buffer comprises an output stage circuit including MOS transistors each having a CMOS structure, for outputting a signal, and an output stage control circuit arranged prior to the output stage circuit. The output stage control circuit includes a pull-up circuit and a pull-down circuit for controlling the gate of the final stage MOS transistor of the MOS transistors so that a speed at which a gate-to-source voltage varies when the final stage MOS transistor is turned on, is slower than a speed at which the gate-to-source voltage varies when the final stage MOS transistor is turned off.
Inventors
- 👤 Toshikazu Sei
- 👤 Yasunori Tanaka
- 👤 Shinji Ochi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:06
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/08; H03K17/00; H03K17/08; H03K17/081; H03K17/0812; H03K17/08122; H03K17/16; H03K17/161; H03K17/162; H03K17/163
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
292 words
A CMOS output buffer comprising: first P- and N-channel MOS transistors whose drains are connected to an output terminal, constituting a final output stage, a source of said first P-channel MOS transistor being connected to a power supply potential and a source of said first N-channel MOS transistor being connected to a ground potential; second P- and N-channel MOS transistors whose gates are connected to each other to receive an input signal and whose drains are connected to a gate of said first P-channel MOS transistor, a source of said second P-channel MOS transistor being connected to a power supply potential; a third P-channel MOS transistor whose source and drain are connected between a source of said second N-channel MOS transistor and a ground potential, a gate of said third P-channel MOS transistor being connected to the ground potential; a third N-channel MOS transistor whose gate is supplied with the input signal, drain is connected to a gate of said first P-channel MOS transistor, and source is connected to the ground potential; fourth N- and P-channel MOS transistors whose gates are connected to each other to receive the input signal and drains are connected to a gate of said first N-channel MOS transistor, a source of said fourth N-channel MOS transistor being connected to a ground potential; a fifth N-channel MOS transistor whose source and drain are connected between a source of said fourth P-channel MOS transistor and a power supply potential, a gate of said fifth N-channel MOS transistor being connected to the power supply potential; and a fifth P-channel MOS transistor whose gate is supplied with the input signal, drain is connected to the gate of said first N-channel MOS transistor, and source is connected to the power supply potential.
Claim 2
Dependent Claim
292 words
A CMOS output buffer comprising: first P- and N-channel MOS transistors whose drains are connected to an output terminal, constituting a final output stage, a source of said first P-channel MOS transistor being connected to a power supply potential and a source of said first N-channel MOS transistor being connected to a ground potential; second P- and N-channel MOS transistors whose gates are connected to each other to receive an input signal and whose drains are connected to a gate of said first P-channel MOS transistor, a source of said second P-channel MOS transistor being connected to a power supply potential; a third P-channel MOS transistor whose source and drain are connected between a source of said second N-channel MOS transistor and a ground potential, a gate of said third P-channel MOS transistor being connected to the ground potential; a third N-channel MOS transistor whose gate is supplied with the input signal, drain is connected to a gate of said first P-channel MOS transistor, and source is connected to the ground potential; fourth N- and P-channel MOS transistors whose gates are connected to each other to receive the input signal and drains are connected to a gate of said first N-channel MOS transistor, a source of said fourth N-channel MOS transistor being connected to a ground potential; a fifth N-channel MOS transistor whose source and drain are connected between a source of said fourth P-channel MOS transistor and a power supply potential, a gate of said fifth N-channel MOS transistor being connected to the power supply potential; and a fifth P-channel MOS transistor whose gate is supplied with the input signal, drain is connected to the gate of said first N-channel MOS transistor, and source is connected to the power supply potential.
Claim 3
Dependent Claim
56 words
The CMOS output buffer according to claim 1, wherein said third P-channel MOS transistor clamps a potential at the source of said second N-channel MOS transistor by a back gate bias effect, and said fifth N-channel MOS transistor clamps a potential at the source of said fourth P-channel MOS transistor by the back gate bias effect.
Claim 4
Dependent Claim
37 words
The CMOS output buffer according to claim 2, wherein said third N-channel MOS transistor and said fifth P-channel MOS transistor each have a driving force which is smaller than that of each of the other MOS transistors.
Claim 5
Dependent Claim
47 words
The CMOS output buffer according to claim 3, wherein said third N-channel MOS transistor continues to turn on after an on-state of said second N-channel MOS transistor is saturated, thereby maximizing a difference in potential between the gate and the source of said first P-channel MOS transistor.
Claim 6
Dependent Claim
47 words
The CMOS output buffer according to claim 3, wherein said fifth P-channel MOS transistor continues to turn on after an on-state of said fifth P-channel MOS transistor is saturated, thereby maximizing a difference in potential between the gate and the source of said first N-channel MOS transistor.
Claim 7
Dependent Claim
167 words
A CMOS output buffer comprising: main drive P- and N-channel MOS transistors whose drains are connected to an output terminal, constituting a final output stage, a source of said main drive P-channel MOS transistor being connected to a power supply potential and a source of said main drive N-channel MOS transistor being connected to a ground potential; and a CMOS inverter circuit whose input node is supplied with an input signal and an output node is connected to a gate of said main drive P-channel MOS transistor, said CMOS inverter circuit being arranged between said power supply potential and said ground potential, and comprising a current path for pulling down the output node of said CMOS inverter circuit, and a P-channel MOS transistor, a source and a drain of which are connected between said current path and said ground potential, for clamping a pull-down potential of the output node of said CMOS inverter circuit, a gate of said P-channel MOS transistor being connected to the ground potential.
Claim 8
Dependent Claim
167 words
A CMOS output buffer comprising: main drive P- and N-channel MOS transistors whose drains are connected to an output terminal, constituting a final output stage, a source of said main drive P-channel MOS transistor being connected to a power supply potential and a source of said main drive N-channel MOS transistor being connected to a ground potential; and a CMOS inverter circuit whose input node is supplied with an input signal and an output node is connected to a gate of said main drive P-channel MOS transistor, said CMOS inverter circuit being arranged between said power supply potential and said ground potential, and comprising a current path for pulling down the output node of said CMOS inverter circuit, and a P-channel MOS transistor, a source and a drain of which are connected between said current path and said ground potential, for clamping a pull-down potential of the output node of said CMOS inverter circuit, a gate of said P-channel MOS transistor being connected to the ground potential.
Claim 9
Dependent Claim
90 words
The CMOS output buffer according to claim 6, wherein said CMOS inverter circuit further comprises an auxiliary N-channel MOS transistor having a driving force which is smaller than that of each of other transistors, for changing the pull-down potential of the output node of said CMOS inverter to a ground potential, a gate of said auxiliary N-channel MOS transistor being supplied with the input signal, a drain thereof being connected to the gate of said main drive P-channel MOS transistor, and a source thereof being connected to the ground potential.
Claim 10
Dependent Claim
168 words
A CMOS output buffer comprising: main drive P- and N-channel MOS transistors whose drains are connected to an output terminal, constituting a final output stage, a source of said main drive P-channel MOS transistor being connected to a power supply potential and a source of said main drive N-channel MOS transistor being connected to a ground potential; and a CMOS inverter circuit whose input node is supplied with an input signal and output node is connected to a gate of said main drive N-channel MOS transistor, said CMOS inverter circuit being arranged between said power supply potential and said ground potential, and comprising a current path for pulling up the output node of said CMOS inverter circuit, and an N-channel MOS transistor, a source and a drain of which are connected between said current path and said power supply potential, for clamping a pull-up potential of the output node of said CMOS inverter circuit, a gate of said N-channel MOS transistor being connected to the power supply potential.
Claim 11
Dependent Claim
168 words
A CMOS output buffer comprising: main drive P- and N-channel MOS transistors whose drains are connected to an output terminal, constituting a final output stage, a source of said main drive P-channel MOS transistor being connected to a power supply potential and a source of said main drive N-channel MOS transistor being connected to a ground potential; and a CMOS inverter circuit whose input node is supplied with an input signal and output node is connected to a gate of said main drive N-channel MOS transistor, said CMOS inverter circuit being arranged between said power supply potential and said ground potential, and comprising a current path for pulling up the output node of said CMOS inverter circuit, and an N-channel MOS transistor, a source and a drain of which are connected between said current path and said power supply potential, for clamping a pull-up potential of the output node of said CMOS inverter circuit, a gate of said N-channel MOS transistor being connected to the power supply potential.
Claim 12
Dependent Claim
93 words
The CMOS output buffer according to claim 8, wherein said CMOS inverter circuit further comprises an auxiliary P-channel MOS transistor having a driving force which is smaller than that of each of the other transistors, for changing the pull-up potential of the output node of said CMOS inverter to a power supply potential, a gate of said auxiliary P-channel MOS transistor being supplied with the input signal, a drain thereof being connected to the gate of said main drive N-channel MOS transistor, and a source thereof being connected to the power supply potential.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-31 | 1996-11-30 | 1997-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-31 | 2000-11-30 | 2001-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-31 | 2004-11-30 | 2005-06-01 | $7700.00 | Window Closed / Lapsed |