Output circuit having a broad dynamic range

Claim 2

A buffer circuit comprising: (a) a series combination of first and second transistors connected between a source of voltage and a ground, each of the first and second transistors having control electrodes respectively said first transistor being identical in conductivity type with said second transistor; (b) an output node provided between said first and second transistors; (c) a first logic gate responsive to an input signal and a high-impedance state requesting signal and producing a first drive signal applied to the control electrode of said first transistor, said first logic gate causing said first transistor to forcibly turn off in the presence of said high-impedance state requesting signal; (d) a second logic gate responsive to a complementary signal of said input signal and said high-impedance state requesting signal and producing a second drive signal applied to the control electrode of said second transistor, said second logic gate causing said second transistor to forcibly turn off in the presence of said high-impedance state requesting signal; (e) booster means coupled to the control electrode of said first transistor and operative to boost up the voltage level of said first drive signal to a voltage level higher than that of said source of voltage, thereby allowing said first transistor to turn-on in a non-saturated region; and (f) clamping means coupled to the control electrode of said first transistor and operative to limit the voltage level of said first drive signal at a preselected value larger than that of a voltage level suppled from said source of voltage.

Claim 3

A buffer circuit as set forth in claim 1, in which said preselected value is larger than the voltage level supplied from said source of voltage by a threshold voltage of said first transistor.

Claim 4

A buffer circuit as set forth in claim 1, in which each of said first and second logic gates performs an NOR function.

Claim 5

A buffer circuit as set forth in claim 1, in which said booster means comprise a delay circuit operative to transmit said first drive signal and introduce a preselected delay in the transmission of said first drive signal for producing a delayed first drive signal, and a capacitor having a first electrode supplied with the delayed first drive signal and a second electrode connected to the control electrode of said first transistor.

Claim 6

A buffer circuit as set forth in claim 4, in which said delay circuit comprises an odd number of logic gates connected in cascade.

Claim 7

A buffer circuit as set forth in claim 4, in which said booster means further comprise an amplifier circuit connected between said delay circuit and said capacitor.

Claim 8

A buffer circuit as set forth in claim 1, in which said clamping means comprise a diode having an anode connected to the control electrode of said first transistor and a cathode connected to said source of voltage.

Claim 9

A buffer circuit as set forth in claim 1, in which said buffer circuit, further comprises compensating means operative to compensate a leakage current so as to maintain said first drive signal at the preselected value .

Claim 10

A buffer circuit as set forth in claim 8, in which said compensating means comprises a third transistor having a drain node supplied with a clock signal and a gate electrode connected to the control electrode of said first transistor, a fourth transistor having a drain node capacitively coupled to a source node of the third transistor, a gate electrode connected to the drain node thereof and a source node connected to the control electrode of said first transistor, a fifth transistor having a source node capacitively coupled to the source node of the third transistor and a gate electrode connected to said source of voltage, and a sixth transistor having a source node connected to a drain node of the fifth transistor, a gate electrode connected to the control electrode of said first transistor and a drain node connected to said source of voltage.

Claim 11

A buffer circuit comprising: (a) a series combination of first and second enhancement-mode n-channel filed effect transistors connected between a source of voltage and a ground, each of the first and second enhancement-mode n-channel field effect transistors having control electrodes, respectively; (b) an output node provided between said first and second enhancement-mode n-channel field effect transistor; (c) a first NOR gate responsive to an input signal and a high-impendance state requesting signal and producing a first drive signal applied to the control electrode of said first enhancement-mode n-channel field effect transistor; (d) a second NOR gate responsive to a complementary signal of said input signal and said high-impedance state requesting signal and producing a second drive signal applied to the control electrode of said second enhancement-mode n-channel field effect transistor; (e) a booster circuit coupled to the control electrode of said first enhancement-mode n-channel field effect transistor, said booster circuit having an odd number of logic gates operative to transmit said first drive signal and introduce a preselected delay in the transmission of the first drive signal for producing a delayed first drive signal, and a capacitor having a first electrode supplied with the delayed first drive signal and a second electrode connected to the control electrode of said first enhancement-mode n-channel field effect transistor, said booster circuit being operative to boost up the voltage level of said first drive signal to a voltage level higher than that of said source of voltage, thereby allowing said first transistor to operate in a non-saturation region; (f) a clamping circuit having an enhancement-mode n-channel field effect transistor connected between said source of voltage and the control electrode of said first enhancement-mode n-channel field effect transistor and provided with a control electrode connected to the control electrode of said first enhancement-mode n-channel field effect transistor, said clamping circuit being operative to limit the voltage level of said first drive signal at a preselected value larger than that of the voltage level supplied from said source of voltage; and (g) a compensating circuit comprising a third transistor having a drain node supplied with a clock signal and a gate electrode connected to the control electrode of said first transistor, a fourth transistor having a drain node capacitively coupled to a source node of the third transistor, a gate electrode connected to the drain node thereof and a source node connected to the control electrode of said first transistor, a fifth transistor having source node capacitively coupled to the source node of the third transistor and a gate electrode connected to said source of voltage, and sixth transistor having a source node connected to a drain node of the fifth transistor, a gate electrode connected to the control electrode of said first transistor and a drain node connected to said source of voltage, said compensating circuit being operative to compensate a leakage current so as to maintain said first drive signal at said preselected value.

Claim 12

A buffer circuit comprising: (a) a series combination of first and second enhancement-mode n-channel filed effect transistors connected between a source of voltage and a ground, each of the first and second enhancement-mode n-channel field effect transistors having control electrodes, respectively; (b) an output node provided between said first and second enhancement-mode n-channel field effect transistor; (c) a first NOR gate responsive to an input signal and a high-impendance state requesting signal and producing a first drive signal applied to the control electrode of said first enhancement-mode n-channel field effect transistor; (d) a second NOR gate responsive to a complementary signal of said input signal and said high-impedance state requesting signal and producing a second drive signal applied to the control electrode of said second enhancement-mode n-channel field effect transistor; (e) a booster circuit coupled to the control electrode of said first enhancement-mode n-channel field effect transistor, said booster circuit having an odd number of logic gates operative to transmit said first drive signal and introduce a preselected delay in the transmission of the first drive signal for producing a delayed first drive signal, and a capacitor having a first electrode supplied with the delayed first drive signal and a second electrode connected to the control electrode of said first enhancement-mode n-channel field effect transistor, said booster circuit being operative to boost up the voltage level of said first drive signal to a voltage level higher than that of said source of voltage, thereby allowing said first transistor to operate in a non-saturation region; (f) a clamping circuit having an enhancement-mode n-channel field effect transistor connected between said source of voltage and the control electrode of said first enhancement-mode n-channel field effect transistor and provided with a control electrode connected to the control electrode of said first enhancement-mode n-channel field effect transistor, said clamping circuit being operative to limit the voltage level of said first drive signal at a preselected value larger than that of the voltage level supplied from said source of voltage; and (g) a compensating circuit comprising a third transistor having a drain node supplied with a clock signal and a gate electrode connected to the control electrode of said first transistor, a fourth transistor having a drain node capacitively coupled to a source node of the third transistor, a gate electrode connected to the drain node thereof and a source node connected to the control electrode of said first transistor, a fifth transistor having source node capacitively coupled to the source node of the third transistor and a gate electrode connected to said source of voltage, and sixth transistor having a source node connected to a drain node of the fifth transistor, a gate electrode connected to the control electrode of said first transistor and a drain node connected to said source of voltage, said compensating circuit being operative to compensate a leakage current so as to maintain said first drive signal at said preselected value.

Claim 13

A buffer circuit comprising: (a) a first field effect transistor coupled between a power voltage terminal receiving a power voltage and an output terminal; (b) a second field effect transistor coupled between said output terminal and a reference voltage terminal receiving a reference voltage, said first field effect transistor being identical in conductivity type with said second field effect transistor; (c) control means responsive to an input signal for generating a first drive signal and a second drive signal complementary to the first drive signal, each of said first and second drive signals selectively assuming a first level near said power voltage and a second level near said reference voltage; (d) means for applying said first drive signal to a gate of said first field effect transistor; (e) means for applying said second drive signal to a gate of said second field effect transistor; and (f) a leak compensation circuit coupled to the gate of said first field effect transistor for operatively raising a potential at the gate of the first field effect transistor to a voltage higher than said power voltage only when the first drive signal assumes the first level.

Claim 14

A buffer circuit comprising: (a) a first field effect transistor coupled between a power voltage terminal receiving a power voltage and an output terminal; (b) a second field effect transistor coupled between said output terminal and a reference voltage terminal receiving a reference voltage, said first field effect transistor being identical in conductivity type with said second field effect transistor; (c) control means responsive to an input signal for generating a first drive signal and a second drive signal complementary to the first drive signal, each of said first and second drive signals selectively assuming a first level near said power voltage and a second level near said reference voltage; (d) means for applying said first drive signal to a gate of said first field effect transistor; (e) means for applying said second drive signal to a gate of said second field effect transistor; and (f) a leak compensation circuit coupled to the gate of said first field effect transistor for operatively raising a potential at the gate of the first field effect transistor to a voltage higher than said power voltage only when the first drive signal assumes the first level.

Claim 15

A buffer circuit as set forth in claim 11, in which said lead compensation circuit comprises a series combination of third, fourth and fifth field effect transistors coupled between said power voltage terminal and the gate of said first field effect transistor, and a series combination of a sixth field effect transistor and a capacitor coupled between a clock terminal and a node between said fourth and fifth field effect transistors, said third and sixth field effect transistors having respective gates coupled to the gate of said first field effect transistor, said fourth and fifth field effect transistor having respective gates coupled to said power voltage terminal and said node, respectively, wherein a clock signal is applied to said clock terminal when said first drive signal assumes the first level.

Claim 16

A buffer circuit as set forth in claim 11, in which said control means comprises a booster circuit operative to boost up the voltage level of said first drive signal.

Claim 17

A buffer circuit as set forth in claim 11, in which said buffer circuit further comprises a clamping diode operative to limit the voltage level of said first drive signal at said first level.