CMIS circuit and its driver

Claim 2

A semiconductor integrated circuit comprising: a complementary MIS circuit; said complementary MIS circuit including a first PMIS transistor and a first NMIS transistor; a drain electrode of said first PMIS transistor and a drain electrode of said first NMIS transistor being connected in common to an output terminal of the semiconductor integrated circuit; a driving level-shift circuit; said driving level-shift circuit including a second PMIS transistor having its drain electrode grounded and having its source electrode connected to a V DD voltage supply terminal through a first resistor, and a second NMIS transistor having its drain electrode connected directly to the V DD voltage supply terminal and having its source electrode grounded through a second resistor; a gate electrode of said second NMIS transistor being connected to a gate electrode of said second PMIS transistor; a gate electrode of said first PMIS transistor is connected to a source electrode of said second PMIS transistor; a gate electrode of said first NMIS transistor is connected to a source electrode of said second NMIS transistor; and an input voltage is applied to the interconnected gate electrodes of said second PMIS transistor and said second NMIS transistor.

Claim 3

A semiconductor integrated circuit according to claim 1 wherein: said second PMIS transistor and second NMIS transistor which form said level-shift circuit each have a gate-source threshold voltage; and said second PMIS transistor and said second NMIS transistor being effective for shifting the level of said input voltage an amount corresponding to said gate-source threshold voltage of each such that when said input voltage rises from a lower level to a higher level, the time at which said first PMIS transistor is turned off is advanced and the time at which said first NMIS transistor is turned on is delayed, and when said input voltage falls from the higher level to the lower level, the time at which said first NMIS transistor is turned off is advanced and the time at which said first PMIS transistor and first NMIS transistor of said complementary MIS circuit are concurrently rendered conductive when said input voltage changes is minimized.

Claim 4

A semiconductor integrated circuit according to claim 1 wherein said first and second PMIS transistors are PMOS transistors, and said first and second NMIS transistors are NMOS transistors.

Claim 5

An electronic circuit comprising: a PMIS transistor; an NMIS transistor; drain of said PMIS transistor and said NMIS transistor being connected together to provide an output from said electronic circuit; a source of said PMIS transistor being connected to a voltage source; a source of said NMIS transistor being connected to ground; means for feeding an input signal to gates of said PMIS transistor and said NMIS transistor; said means for feeding including means for shifting minimum level and a signal waveform of said input signal, fed to said gate of said PMIS transistor, to a voltage higher than ground and the input signal respectively, whereby turn-off of said PMIS transistor is advanced during positive transitions of said input signal and turn-on is delayed during negative transitions of said input signal; and said means for feeding including means for shifting a maximum level and the signal waveform of said input signal, fed to said gate of said NMIS transistor, to a voltage lower than said voltage source and said input signal, whereby turn-on of said NMIS transistor is delayed during positive transitions of said input signal and turn-off is advanced during negative transitions of said input signal, whereby the advance of turn-off of said PMIS transistor and the delay of the turn-on of said NMIS transistor reduces a time during which both said PMIS and said NMIS transistor are turned on simultaneously during said positive transitions, and the delay of turn-on of said PMIS transistor and the advance of turn-off of said NMIS transistor reduces a time during which both said PMIS and said NMIS transistor are turned on simultaneously during said negative transitions.

Claim 6

An electronic circuit comprising: a PMIS transistor; an NMIS transistor; drain of said PMIS transistor and said NMIS transistor being connected together to provide an output from said electronic circuit; a source of said PMIS transistor being connected to a voltage source; a source of said NMIS transistor being connected to ground; means for feeding an input signal to gates of said PMIS transistor and said NMIS transistor; said means for feeding including means for shifting minimum level and a signal waveform of said input signal, fed to said gate of said PMIS transistor, to a voltage higher than ground and the input signal respectively, whereby turn-off of said PMIS transistor is advanced during positive transitions of said input signal and turn-on is delayed during negative transitions of said input signal; and said means for feeding including means for shifting a maximum level and the signal waveform of said input signal, fed to said gate of said NMIS transistor, to a voltage lower than said voltage source and said input signal, whereby turn-on of said NMIS transistor is delayed during positive transitions of said input signal and turn-off is advanced during negative transitions of said input signal, whereby the advance of turn-off of said PMIS transistor and the delay of the turn-on of said NMIS transistor reduces a time during which both said PMIS and said NMIS transistor are turned on simultaneously during said positive transitions, and the delay of turn-on of said PMIS transistor and the advance of turn-off of said NMIS transistor reduces a time during which both said PMIS and said NMIS transistor are turned on simultaneously during said negative transitions.

Claim 7

An electronic circuit comprising: a PMIS transistor; an NMIS transistor; drains of said PMIS transistor and said NMIS transistor being connected together to provide an output from said electronic circuit; a source of said PMIS transistor being connected to a voltage source; a source of said NMIS transistor being connected to ground; means for feeding an input signal to gates of said PMIS transistor and said NMIS transistor; said means for feeding including means for shifting a minimum level and a signal waveform of said input signal, fed to said gate of said PMIS transistor, to a voltage higher than ground and the input signal, respectively, whereby turn-off of said PMIS transistor is advanced during positive transitions of said input signal and turn-on is delayed during negative transitions of said input signal; said means for feeding including means for shifting a maximum level and the signal waveform of said input signal, fed to said gate of said NMIS transistor, to a voltage lower than said voltage source and said input signal, whereby turn-on of said NMIS transistor is delayed during positive transitions of said input signal and turn-off is advanced during negative transitions of said input signal, whereby the advance of turn-off of said PMIS transistor and the delay of the turn-on of said NMIS transistor reduces a time which both said PMIS and said NMIS transistor are turned on simultaneously during said positive transitions, and the delay of turn-on of said PMIS transistor and the advance of turn-off of said NMIS transistor reduces a time during which both said PMIS and said NMIS transistor are turned on simultaneously during said negative transitions; and said means for feeding further including: a second PMIS transistor having its source connected through a resistor to a voltage source and having its drain grounded; said input signal being connected to a gate of said second PMIS transistor; and a gate of said PMIS transistor being connected to a junction of said resistor and said source of said second PMIS transistor, whereby a gate threshold of said second PMIS transistor increases a minimum signal voltage fed to said gate of said PMIS transistor.

Claim 8

An electronic circuit comprising: a PMIS transistor; an NMIS transistor; drains of said PMIS transistor and said NMIS transistor being connected together to provide an output from said electronic circuit; a source of said PMIS transistor being connected to a voltage source; a source of said NMIS transistor being connected to ground; means for feeding an input signal to gates of said PMIS transistor and said NMIS transistor; said means for feeding including means for shifting a minimum level and a signal waveform of said input signal, fed to said gate of said PMIS transistor, to a voltage higher than ground and the input signal, respectively, whereby turn-off of said PMIS transistor is advanced during positive transitions of said input signal and turn-on is delayed during negative transitions of said input signal; said means for feeding including means for shifting a maximum level and the signal waveform of said input signal, fed to said gate of said NMIS transistor, to a voltage lower than said voltage source and said input signal, whereby turn-on of said NMIS transistor is delayed during positive transitions of said input signal and turn-off is advanced during negative transitions of said input signal, whereby the advance of turn-off of said PMIS transistor and the delay of the turn-on of said NMIS transistor reduces a time which both said PMIS and said NMIS transistor are turned on simultaneously during said positive transitions, and the delay of turn-on of said PMIS transistor and the advance of turn-off of said NMIS transistor reduces a time during which both said PMIS and said NMIS transistor are turned on simultaneously during said negative transitions; and said means for feeding further including: a second PMIS transistor having its source connected through a resistor to a voltage source and having its drain grounded; said input signal being connected to a gate of said second PMIS transistor; and a gate of said PMIS transistor being connected to a junction of said resistor and said source of said second PMIS transistor, whereby a gate threshold of said second PMIS transistor increases a minimum signal voltage fed to said gate of said PMIS transistor.

Claim 9

Apparatus according to claim 5, wherein said means for feeding further includes: a second NMIS transistor having its drain connected to a voltage source and having its source connected through a resistor to ground; said input signal being connected to a gate of said second NMIS transistor; and a gate of said NMIS transistor being connected to a junction of said resistor and said source of said second NMIS transistor, whereby a gate threshold of said second NMIS transistor decreases a minimum signal voltage fed to said gate of said NMIS transistor.

Claim 10

Apparatus according to claim 4, wherein said electronic circuit is an integrated circuit.

Claim 11

A semiconductor integrated circuit comprising: a complementary pair of transistors consisting of a PMIS transistor and an NMIS transistor; source-drain paths of said PMIS transistor and said NMIS transistor being connected in series between a voltage source and ground; an input terminal for a voltage signal; first means between said input terminal and a gate of said PMIS transistor for increasing a level of a minimum and a signal waveform of said voltage signal fed to said gate of said PMIS transistor; and second means between said input terminal and a gate of said NMIS transistor for decreasing a level of a maximum and said signal waveform of said voltage signal fed to said gate of said NMIS transistor, whereby a time when said PMIS transistor and said NMIS transistor are turned on simultaneously is minimized by said increasing and decreasing of levels.

Claim 12

A semiconductor integrated circuit comprising: a complementary pair of transistors consisting of a PMIS transistor and an NMIS transistor; source-drain paths of said PMIS transistor and said NMIS transistor being connected in series between a voltage source and ground; an input terminal for a voltage signal; first means between said input terminal and a gate of said PMIS transistor for increasing a level of a minimum and a signal waveform of said voltage signal fed to said gate of said PMIS transistor; and second means between said input terminal and a gate of said NMIS transistor for decreasing a level of a maximum and said signal waveform of said voltage signal fed to said gate of said NMIS transistor, whereby a time when said PMIS transistor and said NMIS transistor are turned on simultaneously is minimized by said increasing and decreasing of levels.

Claim 13

A semiconductor integrated circuit comprising: a complementary pair of transistors consisting of a PMIS transistor and an NMIS transistor; source-drain paths of said PMIS transistor and said NMIS transistor being connected in series between a voltage source and ground; an input terminal for a voltage signal; first means between said input terminal and a gate of said PMIS transistor for increasing a level of a minimum and a signal waveform of said voltage signal fed to said gate of said PMIS transistor; said first means including: a second PMIS transistor having its source connected through a resistor to a voltage source and its drain connected to ground; said gate of said PMIS transistor being connected to a junction of said source of said second PMIS transistor and said resistor; and said voltage signal being connected to a gate of said second PMIS transistor; and second means between said input terminal and a gate of said NMIS transistor for decreasing a level of a maximum and said signal waveform of said voltage signal fed to said gate of said NMIS transistor, whereby a time when said PMIS transistor and said NMIS transistor are turned on simultaneously is minimized by said increasing and decreasing of levels.

Claim 14

A semiconductor integrated circuit comprising: a complementary pair of transistors consisting of a PMIS transistor and an NMIS transistor; source-drain paths of said PMIS transistor and said NMIS transistor being connected in series between a voltage source and ground; an input terminal for a voltage signal; first means between said input terminal and a gate of said PMIS transistor for increasing a level of a minimum and a signal waveform of said voltage signal fed to said gate of said PMIS transistor; said first means including: a second PMIS transistor having its source connected through a resistor to a voltage source and its drain connected to ground; said gate of said PMIS transistor being connected to a junction of said source of said second PMIS transistor and said resistor; and said voltage signal being connected to a gate of said second PMIS transistor; and second means between said input terminal and a gate of said NMIS transistor for decreasing a level of a maximum and said signal waveform of said voltage signal fed to said gate of said NMIS transistor, whereby a time when said PMIS transistor and said NMIS transistor are turned on simultaneously is minimized by said increasing and decreasing of levels.

Claim 15

A semiconductor integrated circuit comprising: a complementary pair of transistors consisting of a PMIS transistor and an NMIS transistor; source-drain paths of said PMIS transistor and said NMIS transistor being connected in series between a voltage source and ground; an input terminal for a voltage signal; first means between said input terminal and a gate of said PMIS transistor for increasing a level of a minimum and a signal waveform of said voltage signal fed to said gate of said PMIS transistor; and second means between said input terminal and a gate of said NMIS transistor for decreasing a level of a maximum and said signal waveform of said voltage signal fed to said gate of said NMIS transistor, whereby a time when said PMIS transistor and said NMIS transistor are turned on simultaneously is minimized by said increasing and decreasing of levels; and said second means including: a second NMIS transistor having its source connected through a resistor to ground and its drain connected to said voltage source; said gate of said NMIS transistor being connected to a junction of said source of said second NMIS transistor and said resistor; and said voltage signal being connected to a gate of said second NMIS transistor.

Claim 16

A semiconductor integrated circuit comprising: a complementary pair of transistors consisting of a PMIS transistor and an NMIS transistor; source-drain paths of said PMIS transistor and said NMIS transistor being connected in series between a voltage source and ground; an input terminal for a voltage signal; first means between said input terminal and a gate of said PMIS transistor for increasing a level of a minimum and a signal waveform of said voltage signal fed to said gate of said PMIS transistor; and second means between said input terminal and a gate of said NMIS transistor for decreasing a level of a maximum and said signal waveform of said voltage signal fed to said gate of said NMIS transistor, whereby a time when said PMIS transistor and said NMIS transistor are turned on simultaneously is minimized by said increasing and decreasing of levels; and said second means including: a second NMIS transistor having its source connected through a resistor to ground and its drain connected to said voltage source; said gate of said NMIS transistor being connected to a junction of said source of said second NMIS transistor and said resistor; and said voltage signal being connected to a gate of said second NMIS transistor.