US5059823A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Supply bounce controlled output buffer circuit
Assignee: Advanced Micro Devices Inc
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Filing: 1990-10-22
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Granted: 1991-10-22
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Expires: 2010-10-22
Abstract
Abstract A supply bounce controlled output buffer circuit for producing an output signal at an output terminal pin with a significant reduction in inductive ringing includes an output stage, a first delay network (38), and a second delay network (42). The output stage includes a series-connected pull-up transistor (P1) and pull-down transistor (N1) coupled between a first power supply terminal pin and a second power supply terminal pin. The common connection of the pull-up and pull-down transistors (P1, N1) are coupled to an output terminal pin. The first delay network (38) is interconnected between the first power supply terminal pin and a control electrode of the pull-up transistor (P1) for turning off the pull-up transistor (N1) so as to slow down the rate of rise of the output signal for a portion of the time when the output terminal pin is making a low-to-high transition so as to reduce the overshoot. The second delay network (42) is interconnected between the second power supply terminal pin and a control electrode of the pull-down transistor (N1) for turning off the pull-down transistor (N1) so as to slow down the rate of fall of the output signal for a portion of the time when the output terminal pin is making a high-to-low transition so as to reduce the undershoot.
Inventors
- 👤 Zahid Ahsanullah
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 19:31
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/16; H03K17/161; H03K17/165; H03K17/166; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
254 words
A supply bounce controlled output buffer circuit for producing an output signal at an output terminal pin which has a significant reduction in inductive ringing said output buffer circuit comprising: a first pull-up transistor (P1) having one of its main electrodes coupled to a first power supply terminal pin and its other main electrode coupled to the output terminal pin; a pull-down transistor (N1) having one of its main electrodes coupled to a second power supply terminal pin and its other main electrode coupled to the output terminal pin; a first inverter (34) having its input connected to receive a data input signal and an output; a second inverter (36) having its input connected to the output of said first inverter (34) and an output; a NAND logic gate (40) having a first input connected to the output of said second inverter (36) and an output connected to a control electrode of said pull-up transistor (P1); first delay means (38) having an input connected to said one of its main electrodes of said pull-up transistor (P1) and an output connected to a second input of said NAND logic gate (40); an AND logic gate (44) having a first input connected to the output of said first inverter (34) and an output connected to a control electrode of said pull-down transistor (N1); and second delay means (42) having an input connected to said other main electrode of said pull-down transistor (N1) and an output connected to a second input of said AND logic gate (44).
Claim 2
Dependent Claim
254 words
A supply bounce controlled output buffer circuit for producing an output signal at an output terminal pin which has a significant reduction in inductive ringing said output buffer circuit comprising: a first pull-up transistor (P1) having one of its main electrodes coupled to a first power supply terminal pin and its other main electrode coupled to the output terminal pin; a pull-down transistor (N1) having one of its main electrodes coupled to a second power supply terminal pin and its other main electrode coupled to the output terminal pin; a first inverter (34) having its input connected to receive a data input signal and an output; a second inverter (36) having its input connected to the output of said first inverter (34) and an output; a NAND logic gate (40) having a first input connected to the output of said second inverter (36) and an output connected to a control electrode of said pull-up transistor (P1); first delay means (38) having an input connected to said one of its main electrodes of said pull-up transistor (P1) and an output connected to a second input of said NAND logic gate (40); an AND logic gate (44) having a first input connected to the output of said first inverter (34) and an output connected to a control electrode of said pull-down transistor (N1); and second delay means (42) having an input connected to said other main electrode of said pull-down transistor (N1) and an output connected to a second input of said AND logic gate (44).
Claim 3
Dependent Claim
19 words
An output buffer circuit as claimed in claim 1, wherein said pull-up transistor (Pl) is a P-channel, field-effect transistor.
Claim 4
Dependent Claim
19 words
An output buffer circuit as claimed in claim 2, wherein said pull-down transistor (N1) is an N-channel, field-effect transistor.
Claim 5
Dependent Claim
26 words
An output buffer circuit as claimed in claim 1, wherein said first delay means (38) comprises a first delay network formed of six series-connected inverters (I1-I6).
Claim 6
Dependent Claim
26 words
An output buffer circuit as claimed in claim 4, wherein said second delay means (42) comprises a second delay network formed of five series-connected inverters (I7-I11).
Claim 7
Dependent Claim
22 words
An output buffer circuit as claimed in claim 1, wherein said first delay means (38) comprises any even number of series-connected inverters.
Claim 8
Dependent Claim
22 words
An output buffer circuit as claimed in claim 6, wherein said second delay means (42) comprises any odd number of series-connected inverters.
Claim 9
Dependent Claim
68 words
An output buffer circuit as claimed in claim 1, wherein said pull-down transistor (N1) is responsive to a delayed signal from said second delay means (42) for turning off said pull-down transistor (N1) so as to slow down the rate of fall of the output signal for a portion of the time when said output terminal pin is making the high-to-low transition so as to reduce the undershoot.
Claim 10
Dependent Claim
69 words
An output buffer circuit as claimed in claim 8, wherein said pull-up transistor (Pl) is responsive to a second delayed signal from said first delay means (38) for turning off said pull-up transistor (P1) so as to slow down the rate of rise of the output signal for a portion of the time when said output terminal pin is making the low-to-high transition so as to reduce the overshoot.
Claim 11
Dependent Claim
213 words
A supply bounce controlled output buffer circuit for producing an output signal at an output terminal pin which has a significant reduction in inductive ringing, said output buffer circuit comprising: input means responsive to a data input signal for controlling output stage means; output stage means including a series-connected pull-up transistor (P1) and pull-down transistor (N1) coupled between a first power supply terminal pin and a second power supply terminal pin, the common connection of said pull-up and pull-down transistors (P1,N1) being coupled to an output terminal pin; first delay means (38) interconnected between said first power supply terminal pin and a control electrode of said pull-up transistor (P1) for slowing down the rat of rise of the output signal for a portion of the time when said output terminal pin is making a low-to-high transition so as to reduce the overshoot; said first delay means (38) including a first delay network formed of six series-connected inverters (I1-I6); and second delay means (42) interconnected between said second power supply terminal pin and a control electrode of said pull-down transistor (N1) for slowing down the rate of fall of the output signal for a portion of the time when said output terminal pin is making a high-to-low transition so as to reduce the undershoot.
Claim 12
Dependent Claim
213 words
A supply bounce controlled output buffer circuit for producing an output signal at an output terminal pin which has a significant reduction in inductive ringing, said output buffer circuit comprising: input means responsive to a data input signal for controlling output stage means; output stage means including a series-connected pull-up transistor (P1) and pull-down transistor (N1) coupled between a first power supply terminal pin and a second power supply terminal pin, the common connection of said pull-up and pull-down transistors (P1,N1) being coupled to an output terminal pin; first delay means (38) interconnected between said first power supply terminal pin and a control electrode of said pull-up transistor (P1) for slowing down the rat of rise of the output signal for a portion of the time when said output terminal pin is making a low-to-high transition so as to reduce the overshoot; said first delay means (38) including a first delay network formed of six series-connected inverters (I1-I6); and second delay means (42) interconnected between said second power supply terminal pin and a control electrode of said pull-down transistor (N1) for slowing down the rate of fall of the output signal for a portion of the time when said output terminal pin is making a high-to-low transition so as to reduce the undershoot.
Claim 13
Dependent Claim
19 words
An output buffer circuit as claimed in claim 10, wherein said pull-up transistor (P1) is a P-channel, field-effect transistor.
Claim 14
Dependent Claim
19 words
An output buffer circuit as claimed in claim 11, wherein said pull-down transistor (N1) is an N-channel, field-effect transistor.
Claim 15
Dependent Claim
26 words
An output buffer circuit as claimed in claim 10, wherein said second delay means (42) comprises a second delay network formed of five series-connected inverters (I7-I11).
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-21 | 1995-04-22 | 1995-10-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-21 | 1999-04-22 | 1999-10-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-21 | 2003-04-22 | 2003-10-22 | $7700.00 | Window Closed / Lapsed |