Data processing device for maintaining coherency of data stored in main memory, external cache memory and internal cache memory

Claim 2

A data processing device connected through a system bus to a main memory having contents, an external cache memory storing a selected part of the contents of said main memory and an external device for accessing the system bus, said data processing device including an internal cache memory for storing another selected part of the contents of said main memory, said data processing device comprising: block-in means for fetching one block data from said main memory containing needed data when the needed data is not stored in said internal cache memory; bus release means for releasing said system bus in accordance with a bus request signal output from said external device; block-in break means for stopping the fetching by said block-in means, when said system bus is released during the fetching of said one block data and when write data to be written, due to a write access by said external device, into said main memory coincides with said one block data being fetched; and notification means for determining whether the fetching is being continuously carried out and generating a notification signal indicative of the fetching by the block-in means being stopped by the block-in break means, and said external cache memory stopping subsequent store operations in response to receipt of the notification signal.

Claim 3

A data processing device as claimed in claim 1, wherein said external cache memory stores the one block data transferred to said internal cache memory through said system bus.

Claim 4

A data processing device as claimed in claim 1, wherein said bus release means, said block-in break means and said notification means comprise an address monitor control and block access portion of bus control means.

Claim 5

A data processing device as claimed in claim 1, wherein said external device is a direct memory access controller.

Claim 6

A data processing device as claimed in claim 1, wherein said data are written into said internal cache memory by using a block transfer process.

Claim 7

A data processing device as claimed in claim 1, wherein said block-in means comprises a register and a sequencer connected to said register.

Claim 8

A data processing device as claimed in claim 6, wherein said register is divided into four word blocks.

Claim 9

A data processing device as claimed in claim 6, wherein said sequencer includes counters, a decoder connected to one of said counters, flip-flops connected to said counters, and logic gates connected between said counters and said flip-flops.

Claim 10

A data processing device as claimed in claim 1, wherein said block-in break means comprises a comparator and logic gates connected to said comparator.

Claim 11

A data processing device as claimed in claim 1, wherein said internal cache memory comprises a cache data portion, a write circuit for said cache data portion, a block address portion, and a write circuit for said block address portion.

Claim 12

A data processing device as claimed in claim 1, wherein said block-in means and said internal cache memory comprise memory management means.

Claim 13

A monolithic microprocessor formed in a single semiconductor body, connected to a main memory having contents, an external cache memory and an external device through a system bus, said monolithic microprocessor comprising: instruction control means for controlling fetching, decoding, and executing of instructions; instruction execution means for calculating a operand address and executing an operand operation; memory management means including; an internal cache memory for storing a part of the contents of said main memory; and block-in means for fetching one block data containing needed data from said main memory when the needed data is not stored in said internal cache memory; and bus control means for transferring data among an external device, said external cache memory, said main memory and said monolithic microprocessor through said system bus, said bus control means including: bus release means for releasing said system bus in accordance with a bus request signal output from said external device; block-in break means for stopping the fetching by said block-in means when said system bus is released during the fetching of said one block data and when write data to be written, due to a write access by said external device, into said main memory coincides with said one block data being fetched; and notification means for notifying said external cache memory whether the fetching is being continuously carried out.

Claim 14

A monolithic microprocessor formed in a single semiconductor body, connected to a main memory having contents, an external cache memory and an external device through a system bus, said monolithic microprocessor comprising: instruction control means for controlling fetching, decoding, and executing of instructions; instruction execution means for calculating a operand address and executing an operand operation; memory management means including; an internal cache memory for storing a part of the contents of said main memory; and block-in means for fetching one block data containing needed data from said main memory when the needed data is not stored in said internal cache memory; and bus control means for transferring data among an external device, said external cache memory, said main memory and said monolithic microprocessor through said system bus, said bus control means including: bus release means for releasing said system bus in accordance with a bus request signal output from said external device; block-in break means for stopping the fetching by said block-in means when said system bus is released during the fetching of said one block data and when write data to be written, due to a write access by said external device, into said main memory coincides with said one block data being fetched; and notification means for notifying said external cache memory whether the fetching is being continuously carried out.

Claim 15

A monolithic microprocessor as claimed in claim 12, wherein said external cache memory stores the one block data transferred to said internal cache memory through said system bus.

Claim 16

A monolithic microprocessor as claimed in claim 13, wherein said external cache memory stops subsequent store operations in accordance with a notification signal output from said notification means.

Claim 17

A monolithic microprocessor as claimed in claim 12, wherein said external device comprises a direct memory access controller.

Claim 18

A monolithic microprocessor as claimed in claim 12, wherein said one block data are written into said internal cache memory by using a block transfer process.

Claim 19

A monolithic microprocessor as claimed in claim 12, wherein said block-in means comprises a register and a sequencer connected to said register.

Claim 20

A monolithic microprocessor as claimed in claim 17, wherein said register is divided into four word blocks.

Claim 21

A monolithic microprocessor, as claimed in claim 17, wherein said sequencer includes counters, a decoder connected to one of said counters, flip-flops connected to said counter, and logic gates connected between said counter and said flip-flops.

Claim 22

A monolithic microprocessor as claimed in claim 12, wherein said block-in break means comprises a comparator and logic gates connected to said comparator.

Claim 23

A monolithic microprocessor as claimed in claim 12, wherein said internal cache memory comprises a cache data portion, a write circuit for said cache data portion, a block address portion, and a write circuit for said block address portion.

Claim 24

A data processing device comprising: a main memory; an external cache memory; an external device; a system bus; and a microprocessing unit including an internal cache memory for storing a part of a contents of said main memory, and connected to said main memory, said external cache memory and said external device through said system bus, said microprocessing unit comprising: block-in means for fetching one block data from said main memory containing needed data when the needed data is not stored in said internal cache memory; bus release means for releasing said system bus in accordance with a bus request signal output from said external device; block-in break means for stopping the fetching by said block-in means, when said system bus is released during the fetching of said one block data, and when write data to be written, due to a write access by said external device, into said main memory coincides with said one block data being fetched; and notification means for notifying said external cache means whether the fetching is being continuously carried out.

Claim 25

A data processing device comprising: a main memory; an external cache memory; an external device; a system bus; and a microprocessing unit including an internal cache memory for storing a part of a contents of said main memory, and connected to said main memory, said external cache memory and said external device through said system bus, said microprocessing unit comprising: block-in means for fetching one block data from said main memory containing needed data when the needed data is not stored in said internal cache memory; bus release means for releasing said system bus in accordance with a bus request signal output from said external device; block-in break means for stopping the fetching by said block-in means, when said system bus is released during the fetching of said one block data, and when write data to be written, due to a write access by said external device, into said main memory coincides with said one block data being fetched; and notification means for notifying said external cache means whether the fetching is being continuously carried out.

Claim 26

A data processing system as claimed in claim 22, wherein said external cache memory stores the one block data transferred to said internal cache memory through said system bus.

Claim 27

A data processing device as claimed in claim 23, wherein said external cache memory stops subsequent store operations in accordance with a notification signal output from said notification means.

Claim 28

A data processing device as claimed in claim 22, wherein said external device comprises a direct memory access controller.

Claim 29

A data processing device as claimed in claim 22, wherein said one block data are written into said internal cache memory by a block transfer process.

Claim 30

A data processing device as claimed in claim 22, wherein said block-in means and said internal cache memory comprise a memory management means.

Claim 31

A data processing device as claimed in claim 22, wherein said bus release means, said block-in break means and said notification means comprise an address monitor control and block access portion of bus control means.

Claim 32

A cache control method of avoiding inconsistency among an internal cache memory provided in a microprocessor unit, an external cache memory and a main memory during writing by an external device, where said external cache memory and said main memory are connected to said internal cache memory through a system bus and said external cache memory stores data transferred thereto by said system bus, said cache control method comprising the steps of: fetching one block data from said main memory containing needed data when the needed data is not stored in said internal cache memory; releasing said system bus if not released in accordance with a bus request signal output from said external device; stopping the fetching of said one block data when said system bus is released during the fetching of said one block data, and when write data to be written due to a write access by said external device into said main memory coincides with said one block data being fetched; notifying said external cache memory whether the fetching is being continuously carried; and stopping a store operation by said external cache.

Claim 33

A cache control method of avoiding inconsistency among an internal cache memory provided in a microprocessor unit, an external cache memory and a main memory during writing by an external device, where said external cache memory and said main memory are connected to said internal cache memory through a system bus and said external cache memory stores data transferred thereto by said system bus, said cache control method comprising the steps of: fetching one block data from said main memory containing needed data when the needed data is not stored in said internal cache memory; releasing said system bus if not released in accordance with a bus request signal output from said external device; stopping the fetching of said one block data when said system bus is released during the fetching of said one block data, and when write data to be written due to a write access by said external device into said main memory coincides with said one block data being fetched; notifying said external cache memory whether the fetching is being continuously carried; and stopping a store operation by said external cache.

Claim 34

A cache control method as claimed in claim 29, wherein said one block data are written into said internal cache memory by a block transfer process.