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US5455800A
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Apparatus and a method for improving the program and erase performance of a flash EEPROM memory array
Assignee: Intel Corp
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Filing: 1994-10-27
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Granted: 1995-10-03
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Expires: 2014-10-27
Abstract
Abstract A voltage Vpp is provided for use in programing and erasing transistors which transistors normally switch with a voltage Vpp centering at X volts in a range varying from X plus Y to X minus Y volts. When transistors in an array are selected to operate in this range, a significant number of the blocks of memory transistors require as much as three times as long to program and erase as do typical memory transistors. The invention provides circuitry for furnishing a voltage Vpp to program and erase the blocks of the memory array which voltage is controlled to be in a range of X to X+Y volts and centers around X+1/2 Y volts.
Inventors
- 👤 Steven E. Wells
- 👤 Neal Mielke
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 19:31
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/30
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
168 words
In a flash EEPROM array having a plurality of memory cells, wherein each of the memory cells includes a source, a drain, a control gate, and a floating gate, a method of improving erasure of the memory cells, comprising the steps of: (A) generating a Vpp voltage for erasing the memory cells, wherein due to characteristics variations of the memory cells, some of the memory cells are erased requiring substantially longer than a predetermined time within which other cells of the memory cells are erased if the Vpp voltage varies from X minus Y volts to X volts; (B) applying the Vpp voltage to the source of each of memory cells for erasure; (c) allowing the Vpp voltage to vary only within a range of X volts to X plus Y volts and center around X plus Y/2 volts such that substantially all of the memory cells require the predetermined time to erase regardless of the characteristics variations of the memory cells, wherein Y is less than one.
Claim 2
Dependent Claim
168 words
In a flash EEPROM array having a plurality of memory cells, wherein each of the memory cells includes a source, a drain, a control gate, and a floating gate, a method of improving erasure of the memory cells, comprising the steps of: (A) generating a Vpp voltage for erasing the memory cells, wherein due to characteristics variations of the memory cells, some of the memory cells are erased requiring substantially longer than a predetermined time within which other cells of the memory cells are erased if the Vpp voltage varies from X minus Y volts to X volts; (B) applying the Vpp voltage to the source of each of memory cells for erasure; (c) allowing the Vpp voltage to vary only within a range of X volts to X plus Y volts and center around X plus Y/2 volts such that substantially all of the memory cells require the predetermined time to erase regardless of the characteristics variations of the memory cells, wherein Y is less than one.
Claim 3
Dependent Claim
52 words
The method of claim 1, wherein the step (A) further comprises the step of raising the voltage level of a power supply voltage applied to the flash EEPROM array to generate the Vpp voltage, wherein the voltage level of the Vpp voltage is significantly higher than that of the power supply voltage.
Claim 4
Dependent Claim
48 words
The method of claim 2, further comprising the step of applying the power supply voltage to the memory cells of the flash EEPROM array only when the Vpp voltage is within the range of X volts to X plus Y volts and centering around X plus Y/2 volts.
Claim 5
Dependent Claim
15 words
The method of claim 1, wherein X is 12 and X plus Y is 12.6.
Claim 6
Dependent Claim
248 words
A flash EEPROM, comprising: (A) an array having a plurality of memory cells, each having a source, a drain, a control gate, and a floating gate, wherein the memory cells can be erased by applying a Vpp voltage to the source of each of the memory cells, wherein each of the memory cells has an erasure characteristics that is different from that of another one of the memory cells such that some of the memory cells are erased requiring substantially longer than a predetermined time within which other cells of the memory cells are erased when the Vpp voltage varies from X minus Y volts to X volts; (B) a precision voltage generation circuit coupled to receive a power supply voltage for generating and applying the Vpp voltage to the source of each of the memory cells for erasure, wherein the precision voltage generation circuit further comprises (i) a voltage pump circuit coupled to receive the power supply voltage for generating the Vpp voltage, wherein the voltage level of the Vpp voltage is significantly higher than that of the power supply voltage; (ii) a control circuit for controlling the voltage pump circuit to allow the Vpp voltage to vary only within a range of X to X plus Y volts and center around X plus Y/2 volts such that substantially all of the memory cells require the predetermined time to erase regardless of the erasure characteristics of each of the memory cells, wherein Y is less than one.
Claim 7
Dependent Claim
248 words
A flash EEPROM, comprising: (A) an array having a plurality of memory cells, each having a source, a drain, a control gate, and a floating gate, wherein the memory cells can be erased by applying a Vpp voltage to the source of each of the memory cells, wherein each of the memory cells has an erasure characteristics that is different from that of another one of the memory cells such that some of the memory cells are erased requiring substantially longer than a predetermined time within which other cells of the memory cells are erased when the Vpp voltage varies from X minus Y volts to X volts; (B) a precision voltage generation circuit coupled to receive a power supply voltage for generating and applying the Vpp voltage to the source of each of the memory cells for erasure, wherein the precision voltage generation circuit further comprises (i) a voltage pump circuit coupled to receive the power supply voltage for generating the Vpp voltage, wherein the voltage level of the Vpp voltage is significantly higher than that of the power supply voltage; (ii) a control circuit for controlling the voltage pump circuit to allow the Vpp voltage to vary only within a range of X to X plus Y volts and center around X plus Y/2 volts such that substantially all of the memory cells require the predetermined time to erase regardless of the erasure characteristics of each of the memory cells, wherein Y is less than one.
Claim 8
Dependent Claim
41 words
The flash EEPROM of claim 5, wherein precision voltage generation circuit further comprises a comparator circuit for applying the power supply voltage to the array when the Vpp voltage generated is within the range of X to X plus Y volts.
Claim 9
Dependent Claim
16 words
The flash EEPROM of claim 5, wherein X is 12 and X plus Y is 12.6.
References Cited (Backward Citations)
US4710647A
Cited
US4888738A
Cited
EP0392895B1
Cited
US5265052A
Cited
GB2251323A
Cited
GB2251324A
Cited
US5295113A
Cited
US5255224A
Cited
CA2088442A1
Cited
US5313429A
Cited
US5267218A
Cited
US5274599A
Cited
US5331592A
Cited
US5357463A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-10-02 | 1999-04-03 | 1999-10-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-10-02 | 2003-04-03 | 2003-10-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-10-02 | 2007-04-03 | 2007-10-03 | $7700.00 | Window Closed / Lapsed |