Flash memory source inhibit generator

Claim 2

An electrically erasable and electrically programmable read-only memory fabricated on a silicon substrate and employing a plurality of memory cells arranged in blocks each memory cell having a floating gate, an improvement for maintaining the state of said cells in blocks not presently being programmed comprising: first and second bias potentials, said first bias potential being lower than a programming potential and said second bias potential being lower than said first potential; first, second and third transistors coupled in series between said programming potential and ground, said first and third transistors being matched one to another, the gate of said first transistor being coupled to said first bias potential, the gate of the third transistor being coupled to said second bias potential and the gate of said second transistor being coupled to a first node disposed between said first and second transistors, said first and third transistors providing a first potential at said first node disposed between said first and said second transistor; fourth and fifth matched transistors coupled in series between a reading potential and ground, the gate of said fourth transistor coupled to said first node and the gate of said fifth transistor coupled to the gate of said third transistor such that the gate of said fourth transistor is approximately at said first potential and the gate of said fifth transistor is at said second bias potential, said fourth and fifth transistors providing a second potential at a second node disposed between said fourth and fifth transistors, switch means for switching the source of said cells in blocks not presently being programmed to said second potential if cells in other blocks are presently being programmed.

Claim 3

The improvement defined by claim 1 wherein said silicon substrate is of a first conductivity type and said first and third transistors are formed in wells of a second conductivity type.

Claim 4

The improvement defined by claim 2 wherein said first and second bias potentials comprise resistive means formed in said silicon substrate in a region of said second conductivity type and coupled between said programming potential and ground.

Claim 5

The improvement defined by claim 3 wherein said first, third and fifth transistors are comprised of p-type field-effect transistors.

Claim 6

The improvement defined by claim 4 wherein said second and fourth transistors are comprised of n-type field-effect transistors.

Claim 7

The improvement defined by claim 2 wherein the second bias potential is ground.

Claim 8

The improvement of claim 5 wherein said improvement may be switched off if no blocks are being programmed.

Claim 9

An electrically erasable and electrically programmable read-only memory fabricated on a silicon substrate and having a plurality of memory cells arranged in blocks each memory cell having a floating gate, an improvement for maintaining the state of said cells in blocks not presently being programmed comprising: (i) first circuit means incorporated on said substrate for providing a first potential lower than the potential used to program said cells, said first circuit means comprising: (a) a first field-effect transistor being coupled in series with a second field-effect transistor being coupled in series with a third field-effect transistor, said first field-effect transistor also coupled to a programming potential and matched to said third field-effect transistor, said third field-effect transistor also coupled to a ground potential; (b) a resistor means coupled to said programming potential for developing said first potential and a bias potential, the gates of said first and said third transistors being coupled to said resistor means such that the gate of said first transistor is approximately at said first potential and the gate of said third transistor is at said bias potential, a first node disposed between said first transistor and said second transistor providing said first potential, the gate of said second transistor coupled to said first node such that the gate of said second transistor is also approximately at said first potential, (ii) second circuit means incorporated on said substrate for providing a second potential lower than said first potential, said second circuit comprising: (a) fourth and fifth field-effect transistors coupled in series and matched to one another, said fourth transistor also coupled to a reading potential, said fifth field-effect transistor also coupled to a ground potential, the gate of said fourth transistor being coupled to said first node and the gate of said fifth transistor being coupled to the gate of the third transistor such that the gate of said fourth transistor is approximately at said first potential and the gate of said fifth transistor is at said bias potential; (b) said second potential being provided at a second node disposed between said fourth and fifth transistors, (iii) switch means incorporated on said substrate for switching the source of said cells in blocks not presently being programmed to said second potential if cells in other blocks are presently being programmed.

Claim 10

An electrically erasable and electrically programmable read-only memory fabricated on a silicon substrate and having a plurality of memory cells arranged in blocks each memory cell having a floating gate, an improvement for maintaining the state of said cells in blocks not presently being programmed comprising: (i) first circuit means incorporated on said substrate for providing a first potential lower than the potential used to program said cells, said first circuit means comprising: (a) a first field-effect transistor being coupled in series with a second field-effect transistor being coupled in series with a third field-effect transistor, said first field-effect transistor also coupled to a programming potential and matched to said third field-effect transistor, said third field-effect transistor also coupled to a ground potential; (b) a resistor means coupled to said programming potential for developing said first potential and a bias potential, the gates of said first and said third transistors being coupled to said resistor means such that the gate of said first transistor is approximately at said first potential and the gate of said third transistor is at said bias potential, a first node disposed between said first transistor and said second transistor providing said first potential, the gate of said second transistor coupled to said first node such that the gate of said second transistor is also approximately at said first potential, (ii) second circuit means incorporated on said substrate for providing a second potential lower than said first potential, said second circuit comprising: (a) fourth and fifth field-effect transistors coupled in series and matched to one another, said fourth transistor also coupled to a reading potential, said fifth field-effect transistor also coupled to a ground potential, the gate of said fourth transistor being coupled to said first node and the gate of said fifth transistor being coupled to the gate of the third transistor such that the gate of said fourth transistor is approximately at said first potential and the gate of said fifth transistor is at said bias potential; (b) said second potential being provided at a second node disposed between said fourth and fifth transistors, (iii) switch means incorporated on said substrate for switching the source of said cells in blocks not presently being programmed to said second potential if cells in other blocks are presently being programmed.

Claim 11

The improvement defined by claim 8 wherein said silicon substrate is of a first conductivity type and said first and third transistors are formed in wells of a second conductivity type.

Claim 12

The improvement defined by claim 9 wherein said resistor means comprises a resistor formed in said silicon substrate in a region of said second conductivity type.

Claim 13

The improvement defined by claim 10 wherein said first, third and fifth transistors are comprised of p-type field-effect transistors.

Claim 14

The improvement defined by claim 11 wherein said second and fourth transistors are comprised of n-type field-effect transistors.

Claim 15

The improvement of claim 12 wherein said improvement may be switched off if no blocks are being programmed.

Claim 16

A voltage generation means comprising: i) A first resistor having one terminal coupled to a first potential and a second terminal coupled to a first node; ii) a second resistor having one terminal coupled to said first node and a second terminal coupled to a second potential; iii) a first p-type transistor having a drain, a source and a gate, said source of said first p-type transistor coupled to said first potential, said gate of said first p-type transistor coupled to said first node and said drain of said first p-type transistor coupled to a second node; iv) a first n-type transistor having a drain, a source and a gate, said drain of said first n-type transistor coupled to said second node, said gate of said first n-type transistor coupled to said second node and said source of said first n-type transistor coupled to a third node; v) a second p-type transistor matched to said first p-type transistor, said second p-type transistor having a drain, a source and a gate, said source of said second p-type transistor coupled to said third node, said gate of said second p-type transistor coupled to said second potential and said drain of said second p-type transistor coupled to said second potential; vi) a second n-type transistor having a drain, a source and a gate, said drain of said second n-type transistor coupled to a third potential, said gate of said second n-type transistor coupled to said second node and said source of said second n-type transistor coupled to a fourth node; vii) a third p-type transistor matched to said second p-type transistor, said third p-type transistor having a drain, a source and a gate, said source of said third p-type transistor coupled to said fourth node, said gate of said third n-type transistor coupled to said second potential and said drain of said third p-type transistor coupled to said second potential; wherein said fourth node is an output node of the voltage generation means.

Claim 17

A voltage generation means comprising: i) A first resistor having one terminal coupled to a first potential and a second terminal coupled to a first node; ii) a second resistor having one terminal coupled to said first node and a second terminal coupled to a second potential; iii) a first p-type transistor having a drain, a source and a gate, said source of said first p-type transistor coupled to said first potential, said gate of said first p-type transistor coupled to said first node and said drain of said first p-type transistor coupled to a second node; iv) a first n-type transistor having a drain, a source and a gate, said drain of said first n-type transistor coupled to said second node, said gate of said first n-type transistor coupled to said second node and said source of said first n-type transistor coupled to a third node; v) a second p-type transistor matched to said first p-type transistor, said second p-type transistor having a drain, a source and a gate, said source of said second p-type transistor coupled to said third node, said gate of said second p-type transistor coupled to said second potential and said drain of said second p-type transistor coupled to said second potential; vi) a second n-type transistor having a drain, a source and a gate, said drain of said second n-type transistor coupled to a third potential, said gate of said second n-type transistor coupled to said second node and said source of said second n-type transistor coupled to a fourth node; vii) a third p-type transistor matched to said second p-type transistor, said third p-type transistor having a drain, a source and a gate, said source of said third p-type transistor coupled to said fourth node, said gate of said third n-type transistor coupled to said second potential and said drain of said third p-type transistor coupled to said second potential; wherein said fourth node is an output node of the voltage generation means.

Claim 18

The voltage generation means of claim 14 wherein said first potential is approximately +12 volts.

Claim 19

The voltage generation means of claim 15 wherein said second potential is ground potential.

Claim 20

The voltage generation means of claim 16 wherein said third potential is approximately +5 volts.

Claim 21

The voltage generation means of claim 17 wherein said voltage generation output fourth node is at a potential of approximately +2 volts.

Claim 22

The voltage generation means of claim 18 further comprising a means for switching said output node of said voltage generation means.

Claim 23

The voltage generation means of claim 19 wherein said switching means comprises a Not OR (NOR) gate having as a first input a block select signal and a second input an inverted voltage generation enable signal.

Claim 24

The voltage generation means of claim 19 wherein said switching means comprises one transistor associated with each said block, each said transistor being of an adequate size to allow the source inhibit potential rise time for the associated block to approximately match the source inhibit potential rise time of all other blocks.

Claim 25

The improvement of claim 18 wherein said improvement may be switched off if no blocks are being programmed.