Polyphase clock generation circuit

Claim 2

A polyphase clock generation circuit comprising: a first power source voltage terminal; a second power source voltage terminal; a first clock driver including a P-channel field-effect transistor with a source connected to the first power source voltage terminal, and an N-channel field-effect transistor with a source connected to the second power source voltage terminal and a drain connected to a drain of the P-channel field-effect transistor, said first clock driver producing a first clock signal; a second clock driver including a P-channel field-effect transistor with a source connected to the first power source voltage terminal, and an N-channel field-effect transistor with a source connected to the second power source voltage terminal and a drain connected to a drain of the P-channel field-effect transistor, said second clock driver producing a second clock signal; and clock driver driving means for turning on the P-channel field-effect transistor and the N-channel field-effect transistor of said first and second clock drivers alternately and independently of each other so that the P-channel field-effect transistor and the N-channel field-effect transistor may not have an ON-state simultaneously with each other, said clock driver driving means including delay means interconnecting said first and second clock drivers so that the first clock signal and the second clock signal do not present an overlapping condition of high level.

Claim 3

The polyphase clock generation circuit as claimed in claim 1 wherein the second power source voltage terminal is grounded.

Claim 4

A polyphase clock generation circuit comprising: a first power source voltage terminal; a second power source voltage terminal; inverting means for inverting a polarity of a single-phase clock to produce an inverted clock; first logical AND means; first logical OR means; second logical AND means; second logical OR means; a first clock driver including a first P-channel field-effect transistor with a gate to which the output signal of the first logical AND means is inputted and a source connected to the first power source voltage terminal, and a first N-channel field-effect transistor with a gate to which the output signal of the first logical OR means is inputted, a source connected to the second power source voltage terminal, and a drain connected to a drain of the first P-channel field-effect transistor; a second clock driver including a second P-channel field-effect transistor with a gate to which the output signal of the second logical AND means is inputted and a source connected to the first power source voltage terminal, and a second N-channel field-effect transistor with a gate to which the output signal of the second logical OR means is inputted, a source connected to the second power source voltage terminal, and a drain connected to a drain of the second P-channel field-effect transistor; first delay means for delaying the output signal of the first logical OR means by a predetermined first delay time; and second delay means for delaying the output signal of the second logical OR means by a predetermined second delay time; the single-phase clock and the output signal of the second delay means being inputted to the first logical AND means and the first logical OR means; and the inverted clock outputted from the inverting means and the output signal of the first delay means being inputted to the second logical AND means and the second logical OR means.

Claim 5

A polyphase clock generation circuit comprising: a first power source voltage terminal; a second power source voltage terminal; inverting means for inverting a polarity of a single-phase clock to produce an inverted clock; first logical AND means; first logical OR means; second logical AND means; second logical OR means; a first clock driver including a first P-channel field-effect transistor with a gate to which the output signal of the first logical AND means is inputted and a source connected to the first power source voltage terminal, and a first N-channel field-effect transistor with a gate to which the output signal of the first logical OR means is inputted, a source connected to the second power source voltage terminal, and a drain connected to a drain of the first P-channel field-effect transistor; a second clock driver including a second P-channel field-effect transistor with a gate to which the output signal of the second logical AND means is inputted and a source connected to the first power source voltage terminal, and a second N-channel field-effect transistor with a gate to which the output signal of the second logical OR means is inputted, a source connected to the second power source voltage terminal, and a drain connected to a drain of the second P-channel field-effect transistor; first delay means for delaying the output signal of the first logical OR means by a predetermined first delay time; and second delay means for delaying the output signal of the second logical OR means by a predetermined second delay time; the single-phase clock and the output signal of the second delay means being inputted to the first logical AND means and the first logical OR means; and the inverted clock outputted from the inverting means and the output signal of the first delay means being inputted to the second logical AND means and the second logical OR means.

Claim 6

The polyphase clock generation circuit as claimed in claim 3 wherein the second power source voltage terminal is grounded.

Claim 7

A polyphase clock generation circuit comprising: a first power source voltage terminal; a second power source voltage terminal; inverting means for inverting a polarity of a single-phase clock to produce an inverted clock; first logical AND means; first logical OR means; second logical AND means; second logical OR means; a first clock driver including a first P-channel field-effect transistor with a gate to which the output signal of the first logical AND means is inputted and a source connected to the first power source voltage terminal, and a first N-channel field-effect transistor with a gate to which the output signal of the first logical OR means is inputted, a source connected to the second power source voltage terminal, and a drain connected to a drain of the first P-channel field-effect transistor; a second clock driver including a second P-channel field-effect transistor with a gate to which the output signal of the second logical AND means is inputted and a source connected to the first power source voltage terminal, and a second N-channel field-effect transistor with a gate to which the output signal of the second logical OR means is inputted, a source connected to the second power source voltage terminal, and a drain connected to a drain of the second P-channel field-effect transistor; first delay means for delaying the output signal of the first logical AND means by a predetermined first delay time; and second delay means for delaying the output signal of the second logical AND means by a predetermined second delay time; the single-phase clock and the output signal of the second delay means being inputted to the first logical AND means and the first logical OR means; and the inverted clock outputted from the inverting means and the output signal of the first delay means being inputted to the second logical AND means and the second logical OR means.

Claim 8

A polyphase clock generation circuit comprising: a first power source voltage terminal; a second power source voltage terminal; inverting means for inverting a polarity of a single-phase clock to produce an inverted clock; first logical AND means; first logical OR means; second logical AND means; second logical OR means; a first clock driver including a first P-channel field-effect transistor with a gate to which the output signal of the first logical AND means is inputted and a source connected to the first power source voltage terminal, and a first N-channel field-effect transistor with a gate to which the output signal of the first logical OR means is inputted, a source connected to the second power source voltage terminal, and a drain connected to a drain of the first P-channel field-effect transistor; a second clock driver including a second P-channel field-effect transistor with a gate to which the output signal of the second logical AND means is inputted and a source connected to the first power source voltage terminal, and a second N-channel field-effect transistor with a gate to which the output signal of the second logical OR means is inputted, a source connected to the second power source voltage terminal, and a drain connected to a drain of the second P-channel field-effect transistor; first delay means for delaying the output signal of the first logical AND means by a predetermined first delay time; and second delay means for delaying the output signal of the second logical AND means by a predetermined second delay time; the single-phase clock and the output signal of the second delay means being inputted to the first logical AND means and the first logical OR means; and the inverted clock outputted from the inverting means and the output signal of the first delay means being inputted to the second logical AND means and the second logical OR means.

Claim 9

The polyphase clock generation circuit as claimed in claim 5 wherein the second power source voltage terminal is grounded.

Claim 10

A polyphase clock generation circuit comprising: a first power source voltage terminal; a second power source voltage terminal; inverting means for inverting a polarity of a single-phase clock to produce an inverted clock; first logical AND means; first logical OR means; second logical AND means; second logical OR means; a first clock driver including a first P-channel field-effect transistor with a gate to which the output signal of the first logical AND means is inputted and a source connected to the first power source voltage terminal, and a first N-channel field-effect transistor with a gate to which the output signal of the first logical OR means is inputted, a source connected to the second power source voltage terminal, and a drain connected to a drain of the first P-channel field-effect transistor; a second clock driver including a second P-channel field-effect transistor with a gate to which the output signal of the second logical AND means is inputted and a source connected to the first power source voltage terminal, and a second N-channel field-effect transistor with a gate to which the output signal of the second logical OR means is inputted, a source connected to the second power source voltage terminal, and a drain connected to a drain of the second P-channel field-effect transistor; first variable delay means for delaying the output signal of the first logical OR means by a first delay time; and second variable delay means for delaying the output signal of the second logical OR means by a second delay time; the single-phase clock and the output signal of the second variable delay means being inputted to the first logical AND means and the first logical OR means; and the inverted clock outputted from the inverting means and the output signal of the first variable delay means being inputted to the second logical AND means and the second logical OR means.

Claim 11

A polyphase clock generation circuit comprising: a first power source voltage terminal; a second power source voltage terminal; inverting means for inverting a polarity of a single-phase clock to produce an inverted clock; first logical AND means; first logical OR means; second logical AND means; second logical OR means; a first clock driver including a first P-channel field-effect transistor with a gate to which the output signal of the first logical AND means is inputted and a source connected to the first power source voltage terminal, and a first N-channel field-effect transistor with a gate to which the output signal of the first logical OR means is inputted, a source connected to the second power source voltage terminal, and a drain connected to a drain of the first P-channel field-effect transistor; a second clock driver including a second P-channel field-effect transistor with a gate to which the output signal of the second logical AND means is inputted and a source connected to the first power source voltage terminal, and a second N-channel field-effect transistor with a gate to which the output signal of the second logical OR means is inputted, a source connected to the second power source voltage terminal, and a drain connected to a drain of the second P-channel field-effect transistor; first variable delay means for delaying the output signal of the first logical OR means by a first delay time; and second variable delay means for delaying the output signal of the second logical OR means by a second delay time; the single-phase clock and the output signal of the second variable delay means being inputted to the first logical AND means and the first logical OR means; and the inverted clock outputted from the inverting means and the output signal of the first variable delay means being inputted to the second logical AND means and the second logical OR means.

Claim 12

The polyphase clock generation circuit as claimed in claim 7 wherein the second power source voltage terminal is grounded.

Claim 13

The polyphase clock generation circuit as claimed in claim 7 further comprising delay time setting means for setting the first delay time of the first variable delay means and the second delay time of the second variable delay means.

Claim 14

The polyphase clock generation circuit as claimed in claim 9 wherein the second power source voltage terminal is grounded.

Claim 15

A polyphase clock generation circuit comprising: a first power source voltage terminal; a second power source voltage terminal; inverting means for inverting a polarity of a single-phase clock to produce an inverted clock; first logical AND means; first logical OR means; second logical AND means; second logical OR means; a first clock driver including a first P-channel field-effect transistor with a gate to which the output signal of the first logical AND means is inputted and a source connected to the first power source voltage terminal, and a first N-channel field-effect transistor with a gate to which the output signal of the first logical OR means is inputted, a source connected to the second power source voltage terminal, and a drain connected to a drain of the first P-channel field-effect transistor; a second clock driver including a second P-channel field-effect transistor with a gate to which the output signal of the second logical AND means is inputted and a source connected to the first power source voltage terminal, and a second N-channel field-effect transistor with a gate to which the output signal of the second logical OR means is inputted, a source connected to the second power source voltage terminal, and a drain connected to the drain of the second P-channel field-effect transistor; first variable delay means for delaying the output signal of the first logical AND means by a first delay time; and second variable delay means for delaying the output signal of the second logical AND means by a second delay time; the single-phase clock and the output signal of the second variable delay means being inputted to the first logical AND means and the first logical OR means; and the inverted clock outputted from the inverting means and the output signal of the first variable delay means being inputted to the second logical AND means and the second logical OR means.

Claim 16

A polyphase clock generation circuit comprising: a first power source voltage terminal; a second power source voltage terminal; inverting means for inverting a polarity of a single-phase clock to produce an inverted clock; first logical AND means; first logical OR means; second logical AND means; second logical OR means; a first clock driver including a first P-channel field-effect transistor with a gate to which the output signal of the first logical AND means is inputted and a source connected to the first power source voltage terminal, and a first N-channel field-effect transistor with a gate to which the output signal of the first logical OR means is inputted, a source connected to the second power source voltage terminal, and a drain connected to a drain of the first P-channel field-effect transistor; a second clock driver including a second P-channel field-effect transistor with a gate to which the output signal of the second logical AND means is inputted and a source connected to the first power source voltage terminal, and a second N-channel field-effect transistor with a gate to which the output signal of the second logical OR means is inputted, a source connected to the second power source voltage terminal, and a drain connected to the drain of the second P-channel field-effect transistor; first variable delay means for delaying the output signal of the first logical AND means by a first delay time; and second variable delay means for delaying the output signal of the second logical AND means by a second delay time; the single-phase clock and the output signal of the second variable delay means being inputted to the first logical AND means and the first logical OR means; and the inverted clock outputted from the inverting means and the output signal of the first variable delay means being inputted to the second logical AND means and the second logical OR means.

Claim 17

The polyphase clock generation circuit as claimed in claim 11 wherein the second power source voltage terminal is grounded.

Claim 18

The polyphase clock generation circuit as claimed in claim 11, further comprising delay time setting means for setting the first delay time of the first variable delay means and the second delay time of the second variable delay means.

Claim 19

The polyphase clock generation circuit as claimed in claim 13 wherein the second power source voltage terminal is grounded.

Claim 20

A polyphase clock generation circuit comprising: a first power source voltage terminal; a second power source voltage terminal; frequency dividing means for dividing a frequency of a single-phase clock to produce a plurality of divided frequency signals; and a plurality of outputting means each including first logical AND means, second logical AND means, logical OR means, delay means for delaying the output signal of the logical OR means by a predetermined delay time, and a clock driver having a P-channel field-effect transistor with a gate to which the output signal of the first logical AND means is inputted and a source connected to the first power source voltage terminal, and having an N-channel field-effect transistor with a gate to which the output signal of the logical OR means is inputted, a source connected to the second power source voltage terminal, and a drain connected to a drain of the P-channel field-effect transistor; the frequency dividing means producing the plurality of divided frequency signals so that any of the plurality of divided frequency signals has a period of high level which does not overlap with a period of high level of any of the other divided frequency signals; one of the plurality of divided frequency signals generated by the frequency dividing means and the output signals of the delay means which constitute the plurality of outputting means except for one of the plurality of outputting means being inputted to the first logical AND means which constitutes the one of the plurality of outputting means; the output signals of the delay means which constitute the plurality of outputting means except for the one of the plurality of outputting means being inputted to the second logical AND means which constitutes the one of the plurality of outputting means; and the one of the plurality of divided frequency signals generated by the frequency dividing means and the output signal of the second logical AND means being inputted to the logical OR means which constitutes the one of the plurality of outputting means.

Claim 21

A polyphase clock generation circuit comprising: a first power source voltage terminal; a second power source voltage terminal; frequency dividing means for dividing a frequency of a single-phase clock to produce a plurality of divided frequency signals; and a plurality of outputting means each including first logical AND means, second logical AND means, logical OR means, delay means for delaying the output signal of the logical OR means by a predetermined delay time, and a clock driver having a P-channel field-effect transistor with a gate to which the output signal of the first logical AND means is inputted and a source connected to the first power source voltage terminal, and having an N-channel field-effect transistor with a gate to which the output signal of the logical OR means is inputted, a source connected to the second power source voltage terminal, and a drain connected to a drain of the P-channel field-effect transistor; the frequency dividing means producing the plurality of divided frequency signals so that any of the plurality of divided frequency signals has a period of high level which does not overlap with a period of high level of any of the other divided frequency signals; one of the plurality of divided frequency signals generated by the frequency dividing means and the output signals of the delay means which constitute the plurality of outputting means except for one of the plurality of outputting means being inputted to the first logical AND means which constitutes the one of the plurality of outputting means; the output signals of the delay means which constitute the plurality of outputting means except for the one of the plurality of outputting means being inputted to the second logical AND means which constitutes the one of the plurality of outputting means; and the one of the plurality of divided frequency signals generated by the frequency dividing means and the output signal of the second logical AND means being inputted to the logical OR means which constitutes the one of the plurality of outputting means.

Claim 22

The polyphase clock generation circuit as claimed in claim 15 wherein the second power source voltage terminal is grounded.

Claim 23

A polyphase clock generation circuit comprising: a first power source voltage terminal; a second power source voltage terminal; frequency dividing means for dividing a frequency of a single-phase clock to produce a plurality of divided frequency signals; and a plurality of outputting means each including first logical AND means, second logical AND means, logical OR means, variable delay means for delaying the output signal of the logical OR means, and a clock driver having a P-channel field-effect transistor with a gate to which the output signal of the first logical AND means is inputted and a source connected to the first power source voltage terminal and having an N-channel field-effect transistor with a gate to which the output signal of the logical OR means is inputted, a source connected to the second power source voltage terminal, and a drain connected to a drain of the P-channel field-effect transistor; the frequency dividing means producing the plurality of divided frequency signals so that any of the plurality of divided frequency signals has a period of high level which does not overlap with a period of high level of any of the other divided frequency signals; one of the plurality of divided frequency signals generated by the frequency dividing means and the output signals of the variable delay means which constitute the plurality of outputting means except for one of the plurality of outputting means being inputted to the first logical AND means which constitutes the one of the plurality of outputting means; the output signals of the variable delay means which constitute the plurality of outputting means except for the one of the plurality of outputting means being inputted to the second logical AND means which constitutes the one of the plurality of outputting means; and the one of the plurality of divided frequency signals generated by the frequency dividing means and the output signal of the second logical AND means being inputted to the logical OR means which constitutes the one of the plurality of outputting means.

Claim 24

A polyphase clock generation circuit comprising: a first power source voltage terminal; a second power source voltage terminal; frequency dividing means for dividing a frequency of a single-phase clock to produce a plurality of divided frequency signals; and a plurality of outputting means each including first logical AND means, second logical AND means, logical OR means, variable delay means for delaying the output signal of the logical OR means, and a clock driver having a P-channel field-effect transistor with a gate to which the output signal of the first logical AND means is inputted and a source connected to the first power source voltage terminal and having an N-channel field-effect transistor with a gate to which the output signal of the logical OR means is inputted, a source connected to the second power source voltage terminal, and a drain connected to a drain of the P-channel field-effect transistor; the frequency dividing means producing the plurality of divided frequency signals so that any of the plurality of divided frequency signals has a period of high level which does not overlap with a period of high level of any of the other divided frequency signals; one of the plurality of divided frequency signals generated by the frequency dividing means and the output signals of the variable delay means which constitute the plurality of outputting means except for one of the plurality of outputting means being inputted to the first logical AND means which constitutes the one of the plurality of outputting means; the output signals of the variable delay means which constitute the plurality of outputting means except for the one of the plurality of outputting means being inputted to the second logical AND means which constitutes the one of the plurality of outputting means; and the one of the plurality of divided frequency signals generated by the frequency dividing means and the output signal of the second logical AND means being inputted to the logical OR means which constitutes the one of the plurality of outputting means.

Claim 25

The polyphase clock generation circuit as claimed in claim 17 wherein the second power source voltage terminal is grounded.

Claim 26

The polyphase clock generation circuit as claimed in claim 17 further comprising delay time setting means for setting delay times of the variable delay means which constitute the plurality of outputting means.

Claim 27

The polyphase clock generation circuit as claimed in claim 19 wherein the second power source voltage terminal is grounded.