EP0254786A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Programmable logic array and gates therefor
Assignee: Advanced Micro Devices Inc
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Filing: 1986-10-31
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Granted: —
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Expires: 2006-10-31
Abstract
Abstract An AND gate (40) includes first and second input leads (42,43) and an output lead (44). The AND gate (40) includes a first N channel MOS ("NMOS") transistor (58) which couples the output lead (44) to ground in response to the signal (IN1) on the first input lead (42) and a second NMOS transistor (60) which couples the output lead (44) to ground in response to the signal (IN2) on the second input lead (43). A buffer (76) having a high output impedance is coupled to the output lead (44) and tends to maintain the output lead (44) in a constant state. When the signal on the first input lead (42) goes high, the first NMOS transistor (58) turns off and a PMOS transistor (64) turns on, thereby coupling the output lead (44) to a high voltage source (V H ) for a predetermined time period. If the second NMOS transistor (60) is off, the resulting pulse causes the AND gate output signal (Vout) to go high. The high impedance buffer (76) maintains the output lead (44) in the high state.
Inventors
- 👤 William E. Moss
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 14:06
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721; H03K19/0008; H03K19/0013; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K5/00; H03K5/003; H03K5/007; H03K5/15; H03K5/151; H03K5/1515
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
112 words
A gate comprising a first input lead for receiving a first input signal, a first voltage supply lead for receiving a first electrical potential, a second voltage supply lead for receiving a second electrical potential, an output lead, and first switch means for coupling the output lead to the first voltage supply lead in response to the first input signal being in a first state, characterized in that second switch means is coupled between the output lead and the second voltage supply lead, the second switch means closing for a first time period and then opening in response to the first input signal going from the first state to a second state.
Claim 2
Dependent Claim
112 words
A gate comprising a first input lead for receiving a first input signal, a first voltage supply lead for receiving a first electrical potential, a second voltage supply lead for receiving a second electrical potential, an output lead, and first switch means for coupling the output lead to the first voltage supply lead in response to the first input signal being in a first state, characterized in that second switch means is coupled between the output lead and the second voltage supply lead, the second switch means closing for a first time period and then opening in response to the first input signal going from the first state to a second state.
Claim 3
Dependent Claim
89 words
A gate as claimed in claim 1 characterized by a second input lead for receiving a second input signal, third switch means for coupling the output lead to the first voltage supply lead in response to said second input signal being in the first state; and fourth switch means coupled between the output lead and the second voltage supply lead, the fourth switch means closing for a second time period and then opening in response to the second input signal going from the first state to the second state.
Claim 4
Dependent Claim
165 words
A gate as claimed in claim 2 characterized by a plurality of additional input leads, each input lead within said plurality receiving an associated input signal, a first plurality of switch means, each switch means within the first plurality of switch means being uniquely associated with one of said additional input leads, each switch means within the first plurality of switch means coupling the output lead to the first voltage supply lead in response to the input signal on the uniquely associated input lead being in the first state, and a second plurality of switch means, each switch means within the second plurality of switch means being uniquely associated with one of the additional input leads, each switch means within the second plurality of switch means selectively coupling the output lead to the second voltage supply lead for a time period and then opening in response to the input signal on the uniquely associated input lead going from the first state to the second state.
Claim 5
Dependent Claim
28 words
A gate as claimed in claim 2 characterized in that the first electrical potential is ground, and the first, second, third and fourth switch means comprise MOS transistors.
Claim 6
Dependent Claim
83 words
A gate as claimed in claim 2 characterized by a first lead for receiving a signal equal to the first input signal, and a second lead for receiving a signal equal to the logical inverse of the first input signal, the signal on the first lead being delayed by a time period relative to the signal on the second lead when the first input signal goes from the first state to the second state, the second switch means closing during said time period.
Claim 7
Dependent Claim
60 words
A gate as claimed in claim 5 characterized in that the second switch means comprises first and second PMOS transistors coupled in series between the output lead and the second voltage supply lead, the gate of the first PMOS transistor being coupled to the first lead, and the gate of the second PMOS transistor being coupled to the second lead.
Claim 8
Dependent Claim
41 words
A gate as claimed in claim 6 characterized in that the first switch means comprises an NMOS transistor coupled between the output lead and said first voltage supply lead, the gate of the NMOS transistor being coupled to the second lead.
Claim 9
Dependent Claim
59 words
A gate as claimed in claim 5 characterized in that the second switch means comprises first and second NMOS transistors coupled in series between the output lead and the second voltage supply lead, the gate of the first NMOS transistor being coupled to the first lead, the gate of the second NMOS transistor being coupled to the second lead.
Claim 10
Dependent Claim
41 words
A gate as claimed in claim 8 characterized in that the first switch means comprises a PMOS transistor coupled between the first voltage supply lead and the output lead, the gate of the PMOS transistor being coupled to said second lead.
Claim 11
Dependent Claim
146 words
A gate comprising a first input lead for receiving a first input signal and an output lead for providing an output signal, characterized by first switch means having a first lead coupled to receive a first electrical potential, the first switch means having a second lead programmably electrically coupled to the output lead, the first switch means closing in response to the first input signal being in a first state, the first switch means opening in response to the first input signal being in a second state, and second switch means having a first lead coupled to receive a second electrical potential, the second switch means having a second lead programmably electrically coupled to the output lead, the second switch means closing for a predetermined time period and then opening in response to the first input signal going from the first state to the second state.
Claim 12
Dependent Claim
146 words
A gate comprising a first input lead for receiving a first input signal and an output lead for providing an output signal, characterized by first switch means having a first lead coupled to receive a first electrical potential, the first switch means having a second lead programmably electrically coupled to the output lead, the first switch means closing in response to the first input signal being in a first state, the first switch means opening in response to the first input signal being in a second state, and second switch means having a first lead coupled to receive a second electrical potential, the second switch means having a second lead programmably electrically coupled to the output lead, the second switch means closing for a predetermined time period and then opening in response to the first input signal going from the first state to the second state.
Claim 13
Dependent Claim
141 words
A gate as claimed in claim 10 characterized by a second input lead for receiving a second input signal, third switch means having a first lead coupled to receive the first electrical potential, the third switch means having a second lead programmably electrically coupled to the output terminal, the third switch means closing in response to the second input signal being in the first state, the third switch means opening in response to the second input signal being in the second state; and fourth switch means having a first lead coupled to receive the second electrical potential, the fourth switch means having a second lead programmably electrically coupled to the output lead, the fourth switch means closing for a predetermined time period and then opening in response to the second input signal going from the first state to the second state.
Claim 14
Dependent Claim
21 words
A gate as claimed in claim 11 characterized in that the first, second, third and fourth switch means comprise MOS transistors.
Claim 15
Dependent Claim
68 words
A gate as claimed in claim 11 characterized by a voltage supply lead for receiving the second electrical potential, the second switch means comprising a first MOS transistor and a second MOS transistor coupled in series between the output lead and the voltage supply lead, the first and second MOS transistors both being closed when the first input signal goes from the first state to the second state.
Claim 16
Dependent Claim
194 words
A gate comprising a first input lead for receiving a first input signal and an output lead for providing an output signal, characterized by first switch means having a first lead coupled to receive a first electrical potential and a second lead coupled to the output lead, the first switch means being programmably electrically coupled to be in either a first mode or a second mode, the first switch means closing in response to the first input signal being in a first state and opening in response to the first input signal being in a second state when the first switch means is in the first mode, the first switch means closing in response to the first input signal being in the second state and opening in response to the first input signal being in the first state when the first switch means is in the second mode, and second switch means having a first lead coupled to receive a second electrical potential and a second lead coupled to the output lead, the second switch means closing for a predetermined time period and then opening in response to the first input signal changing state.
Claim 17
Dependent Claim
194 words
A gate comprising a first input lead for receiving a first input signal and an output lead for providing an output signal, characterized by first switch means having a first lead coupled to receive a first electrical potential and a second lead coupled to the output lead, the first switch means being programmably electrically coupled to be in either a first mode or a second mode, the first switch means closing in response to the first input signal being in a first state and opening in response to the first input signal being in a second state when the first switch means is in the first mode, the first switch means closing in response to the first input signal being in the second state and opening in response to the first input signal being in the first state when the first switch means is in the second mode, and second switch means having a first lead coupled to receive a second electrical potential and a second lead coupled to the output lead, the second switch means closing for a predetermined time period and then opening in response to the first input signal changing state.
Claim 18
Dependent Claim
187 words
A gate as claimed in claim 14 characterized by a second input lead for receiving a second input signal, third switch means having a first lead coupled to receive the first electrical potential and a second lead coupled to the output lead, the third switch means being programmably electrically coupled to be in either a first mode or a second mode, the third switch means closing in response to the second input signal being in the first state and opening in response to the second input signal being the second state when the third switch means is in the first mode, the third switch means closing in response to the second input signal being in the second state and opening in response to the second input signal being in the first state when the third switch means is in said second mode; and fourth switch means having a first lead coupled to receive the second electrical potential and a second lead coupled to the output lead, the fourth switch means closing for a predetermined time and then opening in response to the second input signal changing state.
Claim 19
Dependent Claim
43 words
A gate as claimed in claim 14 characterized in that the second lead of the first switch means is programmably electrically coupled to the output lead and the second lead of the second switch means is programmably electrically coupled to the output lead.
Claim 20
Dependent Claim
114 words
A gate as claimed in claim 14 characterized by a first lead for providing a signal equal to the first input signal; a second lead for providing a signal equal to logical inverse of the first input signal, and a voltage supply lead for receiving the first electrical potential, wherein the first switch means comprises an MOS transistor coupled between the output lead and the voltage supply lead, the gate of the MOS transistor being programmably electrically coupled to the first lead when the first switch means is in the first mode, the gate of the MOS transistor being coupled to the second lead when the first switch means is in the second mode.
Claim 21
Dependent Claim
124 words
A gate as claimed in claim 14 characterized by a voltage supply lead for receiving the first electrical potential, a first lead for providing a first signal equal to the first input signal, a second lead for providing a signal equal to the logical inverse of the first input signal; and a voltage supply lead for recaiving the first electrical potential, the first switch means comprising an MOS transistor coupled between the output lead and the voltage supply lead, the gate of the MOS transistor being coupled to the second lead when the first switch means is in the first mode, and the gate of the MOS transistor being coupled to the first lead when the first switch means is in the second mode.
Claim 22
Dependent Claim
24 words
A gate as claimed in any preceding claim characterized by high output impedance means tending to maintain the output lead in a constant state.
References Cited (Backward Citations)
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