EP0348894A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Output buffer circuit used for stable voltage source
Assignee: NEC Corp
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Filing: 1989-06-27
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Granted: —
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Expires: 2009-06-27
Abstract
Abstract An output buffer circuit according to the present invention has a complementary inverter circuit (70) and a controlling circuit (66) which produces a pair of driving signals (DRV) for shifting the complementary inverter circuit between two levels, and the controlling circuit has a pull-down transistor (80) and a pull-up transistor (81) both shifted from the off-states to the on-states on the way between the two levels, so that the driving signals slowly swing their voltage levels in an early stage but steeply reaches the two levels, thereby eliminating any overlapping from the driving signals for elimination of undesirable concurrent on-states from the complementary inverter circuit.
Inventors
- 👤 Takahiko Urai
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 22:56
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361; H03K19/0008; H03K19/0013; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/0948
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
240 words
An output buffer circuit for a bit of an input signal, comprising a) an output stage formed by a series combination of first and second field effect transistors supplied with a pair of driving signals, respectively, for being complementarily shifted between on-states and off-states and coupled between first and second constant voltage source respectively producing first and second voltage levels different in voltage level from each other, b) an output node provided between said first and second field effect transistors, and c) a controlling stage supplied with the bit of said input signal and operative to produce said driving signals swinging between high and low voltage levels in the same direction in every alternation period, a time delay taking place between the driving signals, characterized in that said controlling stage comprises c-1) driving signal producing means responsive to the bit of said input signal and operative to produce said driving signals, c-2) load means coupled to said driving signal producing means and operative to cause said driving signals to gradually swing between said high and low voltage levels, and c-3) speed controlling means coupled between the gate electrodes of said first and second field effect transistors and said driving signal producing means and operative to slowly vary said driving signals in an early stage of said alternation period and to steeply vary said driving signals in a later stage of said alternation period, thereby preventing said driving signals from overlapping.
Claim 2
Dependent Claim
240 words
An output buffer circuit for a bit of an input signal, comprising a) an output stage formed by a series combination of first and second field effect transistors supplied with a pair of driving signals, respectively, for being complementarily shifted between on-states and off-states and coupled between first and second constant voltage source respectively producing first and second voltage levels different in voltage level from each other, b) an output node provided between said first and second field effect transistors, and c) a controlling stage supplied with the bit of said input signal and operative to produce said driving signals swinging between high and low voltage levels in the same direction in every alternation period, a time delay taking place between the driving signals, characterized in that said controlling stage comprises c-1) driving signal producing means responsive to the bit of said input signal and operative to produce said driving signals, c-2) load means coupled to said driving signal producing means and operative to cause said driving signals to gradually swing between said high and low voltage levels, and c-3) speed controlling means coupled between the gate electrodes of said first and second field effect transistors and said driving signal producing means and operative to slowly vary said driving signals in an early stage of said alternation period and to steeply vary said driving signals in a later stage of said alternation period, thereby preventing said driving signals from overlapping.
References Cited (Backward Citations)
No citation records indexed.
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