Method and structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits

Claim 1

A method of forming interconnections between spaced silicon regions to be connected on a semi-conductor substrate at least one of which silicon regions to be connected is doped, and wherein said semi-conductor has conductive polysilicon gate electrodes, said method comprising, forming a layer of dielectric etch-stop material over the substrate including the silicon regions to be connected and the gate electrodes, providing a layer of intrinsic polysilicon over said etch-stop material including the silicon regions to be connected and the gate electrodes, said layer of intrinsic polysilicon being formed as a separate layer from said silicon regions to be connected and as a separate layer from said gate electrodes and electrically isolated from said gate electrodes and said silicon regions to be connected, selectively etching said intrinsic polysilicon to reveal the etch-stop material at portions of the silicon regions to be connected, removing the revealed etch-stop material to reveal the portions of the silicon regions to be connected; and forming an electrically conducting material interconnecting at least one of said silicon regions at the revealed portion thereof and the remaining intrinsic polysilicon, said intrinsic polysilicon remaining being physically spaced from portions of the silicon regions to be connected, whereby said intrinsic polysilicon is maintained as a separate layer from said silicon regions to be connected and from said gate electrodes.

Claim 2

A method of forming interconnections between spaced silicon regions to be connected on a semi-conductor substrate at least one of which silicon regions to be connected is doped, and wherein said semi-conductor has conductive polysilicon gate electrodes, said method comprising, forming a layer of dielectric etch-stop material over the substrate including the silicon regions to be connected and the gate electrodes, providing a layer of intrinsic polysilicon over said etch-stop material including the silicon regions to be connected and the gate electrodes, said layer of intrinsic polysilicon being formed as a separate layer from said silicon regions to be connected and as a separate layer from said gate electrodes and electrically isolated from said gate electrodes and said silicon regions to be connected, selectively etching said intrinsic polysilicon to reveal the etch-stop material at portions of the silicon regions to be connected, removing the revealed etch-stop material to reveal the portions of the silicon regions to be connected; and forming an electrically conducting material interconnecting at least one of said silicon regions at the revealed portion thereof and the remaining intrinsic polysilicon, said intrinsic polysilicon remaining being physically spaced from portions of the silicon regions to be connected, whereby said intrinsic polysilicon is maintained as a separate layer from said silicon regions to be connected and from said gate electrodes.

Claim 12

A method of forming interconnections between spaced first and second silicon regions and isolating a third silicon region on a semi-conductor substrate, and wherein said semi-conductor has conductive polysilicon gate electrodes, said method comprising: forming an isolating barrier around the third region, forming a layer of dielectric etch-stop material over the substrate including the first and second silicon regions to be connected and the third silicon region and the gate electrodes, providing a layer of intrinsic polysilicon over said etch-stop material including said first and second silicon regions as a separate layer from said silicon regions and as a separate layer from said gate electrodes, selectively etching said intrinsic polysilicon to reveal the etch-stop material at the three regions of the silicon, removing the revealed etch-stop material from at least portions of the three regions of silicon to reveal portions of said three regions of silicon; and forming an electrically conducting material interconnecting said first and second silicon regions at said revealed portions thereof and the remaining polysilicon, and also on said revealed portion of the isolated third region while maintaining said isolating barrier to prevent connection of said electrically conducting material on said third region to the electrically conducting material connecting said first and second regions, said polysilicon interconnecting said first and second regions being physically spaced from portions of said third region, whereby the polysilicon connecting said first and second regions remains as a separate layer therefrom and from said gate electrodes.

Claim 13

A method of forming interconnections between spaced first and second silicon regions and isolating a third silicon region on a semi-conductor substrate, and wherein said semi-conductor has conductive polysilicon gate electrodes, said method comprising: forming an isolating barrier around the third region, forming a layer of dielectric etch-stop material over the substrate including the first and second silicon regions to be connected and the third silicon region and the gate electrodes, providing a layer of intrinsic polysilicon over said etch-stop material including said first and second silicon regions as a separate layer from said silicon regions and as a separate layer from said gate electrodes, selectively etching said intrinsic polysilicon to reveal the etch-stop material at the three regions of the silicon, removing the revealed etch-stop material from at least portions of the three regions of silicon to reveal portions of said three regions of silicon; and forming an electrically conducting material interconnecting said first and second silicon regions at said revealed portions thereof and the remaining polysilicon, and also on said revealed portion of the isolated third region while maintaining said isolating barrier to prevent connection of said electrically conducting material on said third region to the electrically conducting material connecting said first and second regions, said polysilicon interconnecting said first and second regions being physically spaced from portions of said third region, whereby the polysilicon connecting said first and second regions remains as a separate layer therefrom and from said gate electrodes.