Method of making an EEPROM

Claim 1

A method for producing an electrically programmable, electrically erasable floating gate memory cell utilizing a floating gate electrically insulated from a body of semiconductor material of a first conductivity type by a first dielectric layer, and a control gate electrically insulated from said floating gate by a second dielectric layer, said memory cell being programmed and erased by electron tunneling through said second insulating layer, said method comprising: forming said first dielectric layer on a surface of said substrate; forming a first doped region of a second conductivity type, having a first conductivity, in said body of semiconductor material such that a first channel region of said first conductivity type is located adjacent said first doped region; forming said floating gate on said first dielectric layer such that a first portion of said floating gate is disposed over said first doped region of second conductivity type and a second portion of said floating gate is disposed over said first channel region of said first conductivity type; forming a second dielectric layer over said floating gate and over a second channel region of said first conductivity type, wherein said first channel region is located between said first doped region and said second channel reason; forming a control gate over said second dielectric layer above said floating gate and above said second channel region; and forming second and third doped regions of said second conductivity type in said body of said semiconductor material, said second doped region having a second, higher magnitude of conductivity than said first doped region, said second doped region being disposed in said first region of said second conductivity type, and said third doped region being disposed adjacent the second part of said channel region; whereby a portion of said first doped region of said second conductivity type is disposed under said floating gate and retains said first conductivity.

Claim 2

A method for producing an electrically programmable, electrically erasable floating gate memory cell utilizing a floating gate electrically insulated from a body of semiconductor material of a first conductivity type by a first dielectric layer, and a control gate electrically insulated from said floating gate by a second dielectric layer, said memory cell being programmed and erased by electron tunneling through said second insulating layer, said method comprising: forming said first dielectric layer on a surface of said substrate; forming a first doped region of a second conductivity type, having a first conductivity, in said body of semiconductor material such that a first channel region of said first conductivity type is located adjacent said first doped region; forming said floating gate on said first dielectric layer such that a first portion of said floating gate is disposed over said first doped region of second conductivity type and a second portion of said floating gate is disposed over said first channel region of said first conductivity type; forming a second dielectric layer over said floating gate and over a second channel region of said first conductivity type, wherein said first channel region is located between said first doped region and said second channel reason; forming a control gate over said second dielectric layer above said floating gate and above said second channel region; and forming second and third doped regions of said second conductivity type in said body of said semiconductor material, said second doped region having a second, higher magnitude of conductivity than said first doped region, said second doped region being disposed in said first region of said second conductivity type, and said third doped region being disposed adjacent the second part of said channel region; whereby a portion of said first doped region of said second conductivity type is disposed under said floating gate and retains said first conductivity.