US5216268A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Full-featured EEPROM
Assignee: GIANTEC SEMICONDUCTOR Inc (SHANGHAI) Co
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Filing: 1991-09-23
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Granted: 1993-06-01
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Expires: 2011-09-23
Abstract
Abstract Disclosed is a byte-erasable EEPROM memory cell which utilizes a five volt external source and a voltage multiplier circuit to program and erase a floating gate by means of electron tunneling. To prevent collapse of the voltage multiplier circuit a lightly doped drain region is incorporated preventing gate modulated junction breakdown, thereby preventing collapse of the voltage multiplier circuit. In addition, current flow through the channel separating a source region and the lightly doped drain region is controlled by a portion of a control gate and the floating gate, thereby allowing a higher erased cell threshold voltage. Also disclosed is a process for forming the lightly doped drain region by using the control gate as an effective sidewall spacer.
Inventors
- 👤 Ling Chen
- 👤 Tien-Ler Lin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 08:04
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D30/60; H10D30/68; H10D30/681; H10D30/683; H10B; H10B69/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
154 words
A nonvolatile memory cell comprising: a substrate; means for storing an electric charge disposed adjacent said substrate and separated by a first insulating layer; a first doped region disposed in said substrate, said first doped region having a lightly doped portion disposed adjacent said charge storing means and a heavily doped portion; a second doped region disposed in said substrate and spaced from said first doped region, the space between said first doped region and said second doped region defining a channel, a portion of said charge storing means being disposed adjacent a first portion of said channel; and a conductive body disposed adjacent said second doped region and a second portion of said channel; wherein current passes through said first channel portion only when said charge storing means is at a first predetermined potential and current passes through said second channel portion only when said conductive body is at a second predetermined potential.
Claim 2
Dependent Claim
154 words
A nonvolatile memory cell comprising: a substrate; means for storing an electric charge disposed adjacent said substrate and separated by a first insulating layer; a first doped region disposed in said substrate, said first doped region having a lightly doped portion disposed adjacent said charge storing means and a heavily doped portion; a second doped region disposed in said substrate and spaced from said first doped region, the space between said first doped region and said second doped region defining a channel, a portion of said charge storing means being disposed adjacent a first portion of said channel; and a conductive body disposed adjacent said second doped region and a second portion of said channel; wherein current passes through said first channel portion only when said charge storing means is at a first predetermined potential and current passes through said second channel portion only when said conductive body is at a second predetermined potential.
Claim 3
Dependent Claim
135 words
A nonvolatile memory cell comprising: a substrate; a first doped region disposed in said substrate; a second doped region disposed in said substrate and spaced from said first doped region, the space between said first and second regions defining a channel; a charge storing body disposed adjacent said first doped region and having a portion disposed adjacent said channel; and a conductive body disposed adjacent said second doped region and having a portion disposed adjacent said channel; wherein current passes through said substrate from said first doped region to said second doped region only when said charge storing and conductive bodies are at predetermined potentials; and wherein said first doped region comprises a heavily doped portion and a lightly doped portion, said lightly doped portion being disposed between said channel and said heavily doped portion.
Claim 4
Dependent Claim
135 words
A nonvolatile memory cell comprising: a substrate; a first doped region disposed in said substrate; a second doped region disposed in said substrate and spaced from said first doped region, the space between said first and second regions defining a channel; a charge storing body disposed adjacent said first doped region and having a portion disposed adjacent said channel; and a conductive body disposed adjacent said second doped region and having a portion disposed adjacent said channel; wherein current passes through said substrate from said first doped region to said second doped region only when said charge storing and conductive bodies are at predetermined potentials; and wherein said first doped region comprises a heavily doped portion and a lightly doped portion, said lightly doped portion being disposed between said channel and said heavily doped portion.
Claim 5
Dependent Claim
199 words
A nonvolatile memory cell comprising: a body of semiconductor material of first conductivity type; first, second and third doped regions, each of second conductivity type, extending into said body from a surface, said second doped region having a lightly doped portion and a heavily doped portion; a first channel region disposed between said first doped region and said second doped region, and a second channel region disposed between said second doped region and said third doped region; a first layer of insulating material of a first thickness on said surface above said source, first, second, and third doped regions; a select gate disposed on said first layer above said first doped region; a floating gate disposed on said first layer over a first portion of said second doped region, one end of said floating gate disposed over said lightly doped portion of said second doped region; a second layer of insulating material covering said floating gate; and a control gate having a first section disposed over said floating gate and a second section disposed over a second portion of said second doped region; wherein said floating gate is erased by charging said second doped region with a high voltage.
Claim 6
Dependent Claim
199 words
A nonvolatile memory cell comprising: a body of semiconductor material of first conductivity type; first, second and third doped regions, each of second conductivity type, extending into said body from a surface, said second doped region having a lightly doped portion and a heavily doped portion; a first channel region disposed between said first doped region and said second doped region, and a second channel region disposed between said second doped region and said third doped region; a first layer of insulating material of a first thickness on said surface above said source, first, second, and third doped regions; a select gate disposed on said first layer above said first doped region; a floating gate disposed on said first layer over a first portion of said second doped region, one end of said floating gate disposed over said lightly doped portion of said second doped region; a second layer of insulating material covering said floating gate; and a control gate having a first section disposed over said floating gate and a second section disposed over a second portion of said second doped region; wherein said floating gate is erased by charging said second doped region with a high voltage.
References Cited (Backward Citations)
US5079603A
Cited
US5101250A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-31 | 1996-11-30 | 1997-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-31 | 2000-11-30 | 2001-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-31 | 2004-11-30 | 2005-06-01 | $7700.00 | Window Closed / Lapsed |