Partially resettable, segmented DMA counter

Claim 1

A direct memory access (DMA) controller for a computer system, said direct memory access controller comprising: a) DMA processing means adapted to place a series of data bytes from a selected input device on a data bus for use by a selected output device at selected times, said DMA processing means comprising: means for detecting and communicating an occurrence of an interruption in said placement of said series of data bytes; and b) means, coupled to said DMA processing means, for limiting to a desired number the number of data bytes placed on said data bus, said limiting means comprising: i) a first, byte counter, adapted to count data bytes placed by said DMA processing means, said first, byte counter having signal means for communicating whenever said DMA processing means has placed a first preselected number of data bytes, said signal means resetting said first, byte counter when said interruption in said placement of said series of data byes occurs; ii) a second, block counter coupled to said first, byte counter, said second, block counter changing its count each time said signal means communicates said placement of said first preselected number of data bytes; and means, coupled to said second, block counter, for indicating to said DMA processing means to stop said placement of said series of data bytes on said data bus when said second, block counter reaches a second preselected number; wherein: said DMA processing means resets said first, byte counter and leaves unaffected said second, block counter when said interruption in said placement of said series of data bytes occurs, and said DMA processing means stops said placement of said series of data bytes when said limiting means indicates that said desired number of data bytes has been placed.