File protect circuit and method

Claim 2

In combination with a data processor operating in response to a stored program, a random access storage control unit having a sequentially addressable buffer containing an incrementing address register and having transmission means connected to said buffer for effecting data transfers from the buffer to the processor, a file protection circuit comprising: a detecting means for detecting when said incrementing address register reaches a predetermined value and for producing a compare equal signal when said incrementing address register reaches said predetermined value; blocking means coupled to the transmission means and responsive to said compare equal signal so as to prevent data transfers form said sequentially addressable buffer to said data processor; and counting means for counting the number of blocked data transfers and for producing a stop blocking signal upon reaching a predetermined value, said stop blocking signal being sent to said blocking means to prevent further blocking of subsequent data transfers between said sequentially addressable buffer and said data processor.

Claim 3

The combination of claim 1 additionally comprising, a control means responsive to said stop blocking signal for fetching from said sequentially addressable buffer additional predetermined values for said incrementing address register and said counting means.

Claim 4

blocking data transfers from the sequentially addressable buffer to the data processor when a protected address is detected;

Claim 5

blocking data transfers from the sequentially addressable buffer to the data processor when a protected address is detected;

Claim 6

counting attempted data transfers until the number of attempts equals a predetermined value; and

Claim 7

counting attempted data transfers until the number of attempts equals a predetermined value; and

Claim 8

In combination with a data processor operating in response to a storage program and random access storage control unit having a sequentially addressable buffer containing an incrementing address register and having transmission means connected to said buffer for effecting data transfers from the buffer to the processor, a file protection circuit comprising: a storage register for storing addresses of protected data, said protected data being stored within said sequentially addressable buffer; a comparison circuit connected to said storage register and also connected to said incrementing address register of said sequentially addressable buffer for generating a compare equal signal indicating when the address in said storage register is the same as the address in said incrementing address register; a protect register responsive to said compare equal signal, said protect regIster being in the ON state is response to said compare equal signal; a blocking means responsive to said protect register being in the ON state so as to prevent data transfers from said sequentially addressable buffer to said data processor; and counting means for counting the number of blocked data transfers, said counting means producing a stop block signal to turn said protect register to the OFF state upon reaching a predetermined value whereby subsequent data transfers between said sequentially addressable buffer and said data processor are allowed.

Claim 9

In combination with a data processor operating in response to a storage program and random access storage control unit having a sequentially addressable buffer containing an incrementing address register and having transmission means connected to said buffer for effecting data transfers from the buffer to the processor, a file protection circuit comprising: a storage register for storing addresses of protected data, said protected data being stored within said sequentially addressable buffer; a comparison circuit connected to said storage register and also connected to said incrementing address register of said sequentially addressable buffer for generating a compare equal signal indicating when the address in said storage register is the same as the address in said incrementing address register; a protect register responsive to said compare equal signal, said protect regIster being in the ON state is response to said compare equal signal; a blocking means responsive to said protect register being in the ON state so as to prevent data transfers from said sequentially addressable buffer to said data processor; and counting means for counting the number of blocked data transfers, said counting means producing a stop block signal to turn said protect register to the OFF state upon reaching a predetermined value whereby subsequent data transfers between said sequentially addressable buffer and said data processor are allowed.

Claim 10

The combination of claim 3 additionally comprising a control means responsive to said stop block signal to fetch from said sequentially addressable buffer an additional address of protected data and storing said address of protected data in said storage register and said control means also operative to fetch an additional predetermined value from said sequentially addressable buffer.

Claim 11

allowing data transfers to occur after the predetermined number of attempts have occurred.

Claim 12

allowing data transfers to occur after the predetermined number of attempts have occurred.

Claim 13

repeating the above steps using a new protected address and predetermined count.

Claim 14

repeating the above steps using a new protected address and predetermined count.

Claim 15

In combination with the data processor operating in response to a stored program and a random access storage control unit having a sequentially addressable buffer containing an incrementing address register and having transmission means connected to said buffer for effecting data transfers from the buffer to the processor, a file protection circuit comprising: a storage register for storing addresses of protected data, said protected data being stored within said sequentially addressable buffer; a comparison circuit connected to said storage register and also connected to said incrementing address register of said sequentially addressable buffer for generating a compare equal signal indicating when the address in said storage register is the same as the address in said incrementing address register; a protect register responsive to said compare equal signal, said protect register being in the ON state in response to said compare equal signal; a blocking means responsive to said protect register being in the ON state so as to prevent data transfers from said sequentially addressable buffer to said data processor; and a decrementing count register for storing count data associated with addresses of protected data, said decrementing count register operative to reduce the data stored therein by one whenever said protect register is in the ON state and said incrementing address register is incremented, said decrementing count register producing a count zero signal indicating that the data stored therein has been decremented to zero, said count zero signal operative to put said protect register in the OFF state whereby data transfers from said sequentially addressable buffer to said data processor are prevented only when the protect register is in the ON state.

Claim 16

In combination with the data processor operating in response to a stored program and a random access storage control unit having a sequentially addressable buffer containing an incrementing address register and having transmission means connected to said buffer for effecting data transfers from the buffer to the processor, a file protection circuit comprising: a storage register for storing addresses of protected data, said protected data being stored within said sequentially addressable buffer; a comparison circuit connected to said storage register and also connected to said incrementing address register of said sequentially addressable buffer for generating a compare equal signal indicating when the address in said storage register is the same as the address in said incrementing address register; a protect register responsive to said compare equal signal, said protect register being in the ON state in response to said compare equal signal; a blocking means responsive to said protect register being in the ON state so as to prevent data transfers from said sequentially addressable buffer to said data processor; and a decrementing count register for storing count data associated with addresses of protected data, said decrementing count register operative to reduce the data stored therein by one whenever said protect register is in the ON state and said incrementing address register is incremented, said decrementing count register producing a count zero signal indicating that the data stored therein has been decremented to zero, said count zero signal operative to put said protect register in the OFF state whereby data transfers from said sequentially addressable buffer to said data processor are prevented only when the protect register is in the ON state.

Claim 17

The combination of claim 5 additionally comprising a control means responsive to said count zero signal to fetch from said sequentially addressable buffer an additional address of protected data and storing said address of protected data in said storage register and to fetch from said sequentially addressable buffer count data and storing said count data in said decrementing count register.

Claim 20

The method of claim 7 additionally comprising the step of: