US5451489A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Making and testing an integrated circuit using high density probe points
Assignee: Elm Technology Corp
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Filing: 1993-04-30
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Granted: 1995-09-19
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Expires: 2013-04-30
Abstract
Abstract Each transistor or logic unit on an integrated circuit wafer is tested prior to interconnect metallization. By means of CAD software, the transistor or logic units placement net list is revised to substitute redundant defect-free logic units for defective ones. Then the interconnect metallization is laid down and patterned under control of a CAD computer system. Each die in the wafer thus has its own interconnect scheme, although each die is functionally equivalent, and yields are much higher than with conventional testing at the completed circuit level. The individual transistor or logic unit testing is accomplished by a specially fabricated flexible tester surface made in one embodiment of several layers of flexible silicon dioxide, each layer containing vias and conductive traces leading to thousands of microscopic metal probe points on one side of the test surface. The probe points electrically contact the contacts on the wafer under test by fluid pressure.
Inventors
- 👤 Glenn J. Leedy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 16:44
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/006; G01; G01R; G01R1/00; G01R1/02; G01R1/06; G01R1/067; G01R1/06711; G01R1/06716; G01R1/073; G01R1/07307; G01R1/0735; G01R31/00; G01R31/28; G01R31/282; G01R31/2831; G01R31/316; G01R31/317; G01R31/3181; G01R31/319; G01R31/31903; G01R31/31905; G01R31/31912; G03; G03F; G03F7/00; G03F7/70; G03F7/70425; G03F7/70466; G03F7/70483; G03F7/70605; G03F7/70653; G03F7/70658; H; H10; H10P; H10P74/00; H10P74/23; H10P74/232; G01R1/06755; G01R1/06761; G01R1/07314; G01R31/2851; G01R31/2886; G01R31/2889; H10W; H10W70/00; H10W70/60; H10W70/62; H10W70/63
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
100 words
A method of making an integrated circuit interconnection comprising the steps of: forming a conductive film on a substrate; applying a layer of negative resist over the conductive film; exposing the negative resist layer with a fixed mask, thereby exposing first portions of the resist layer and leaving second portions of the resist layer unexposed; exposing a predetermined area of the resist using an optical stepper without a mask, thereby exposing the second portions of the resist layer within said predetermined area; developing the resist layer; and etching away the conductive film underlying all unexposed portions of the resist layer.
Claim 2
Independent Claim
100 words
A method of making an integrated circuit interconnection comprising the steps of: forming a conductive film on a substrate; applying a layer of negative resist over the conductive film; exposing the negative resist layer with a fixed mask, thereby exposing first portions of the resist layer and leaving second portions of the resist layer unexposed; exposing a predetermined area of the resist using an optical stepper without a mask, thereby exposing the second portions of the resist layer within said predetermined area; developing the resist layer; and etching away the conductive film underlying all unexposed portions of the resist layer.
Claim 3
Dependent Claim
58 words
The method of claim 1, further comprising the steps of: providing a plurality of logic units formed on a surface of the substrate; and testing the logic units to determine which of the logic units are defective; wherein the conductive film underlying said predetermined area of the resist layer is associated with interconnection of the defective logic units.
Claim 4
Dependent Claim
46 words
The method of claim 2 further comprising the steps of removing any remaining portions of the resist layer and patterning the conductive film in an area corresponding to said predetermined area of the resist layer to form logic unit interconnections that bypass the defective logic units.
Claim 5
Dependent Claim
21 words
The method of claim 1, wherein the predetermined area is a rectangle of size less than 100 μm by 100 μm.
Claim 6
Dependent Claim
20 words
The method of claim 1, wherein the predetermined area is less than 1% of a surface area of the substrate.
Claim 7
Dependent Claim
35 words
The method of claim 1 further comprising the steps of removing any remaining portions of the resist layer and patterning the conductive film in in area corresponding to said predetermined area of the resist layer.
Claim 8
Independent Claim
100 words
A method of making an integrated circuit interconnection comprising the steps of: forming a dielectric film on a substrate; applying a layer of negative resist over the dielectric film; exposing the negative resist layer with a fixed mask, thereby exposing first portions of the resist layer and leaving second portions of the resist layer unexposed; exposing a predetermined area of the resist using an optical stepper without a mask, thereby exposing the second portions of the resist layer within said predetermined area; developing the resist layer; and etching away the dielectric film underlying all unexposed portions of the resist layer.
Claim 9
Independent Claim
100 words
A method of making an integrated circuit interconnection comprising the steps of: forming a dielectric film on a substrate; applying a layer of negative resist over the dielectric film; exposing the negative resist layer with a fixed mask, thereby exposing first portions of the resist layer and leaving second portions of the resist layer unexposed; exposing a predetermined area of the resist using an optical stepper without a mask, thereby exposing the second portions of the resist layer within said predetermined area; developing the resist layer; and etching away the dielectric film underlying all unexposed portions of the resist layer.
Claim 10
Dependent Claim
59 words
The method of claim 7, further comprising the steps of: providing a plurality of logic units formed on a surface of the substrate; and testing the logic units to determine which of the logic units are defective; wherein the the conductive film underlying said predetermined area of the resist layer is associated with interconnection of the defective logic units.
Claim 11
Dependent Claim
46 words
The method of claim 8 further comprising the steps of removing any remaining portions of the resist layer and patterning the conductive film in an area corresponding to said predetermined area of the resist layer to form logic unit interconnections that bypass the defective logic units.
Claim 12
Dependent Claim
22 words
The method of claim 7, wherein the predetermined area is a rectangle of a size less than 100 μm by 100 μm.
Claim 13
Dependent Claim
20 words
The method of claim 7, wherein the predetermined area is less than 1% of a surface area of the substrate.
Claim 14
Dependent Claim
35 words
The method of claim 7 further comprising the steps of removing any remaining portions of the resist layer and patterning the conductive film in an area corresponding to said predetermined area of the resist layer.
Claim 15
Independent Claim
124 words
A method of making an integrated circuit interconnection comprising the steps of: forming a conductive film on a substrate; applying a layer of positive optical resist over the film; exposing the resist layer by use of a fixed mask, thereby exposing first portions of the resist layer and leaving second portions of the resist layer unexposed; exposing a predetermined area of the resist layer by an optical stepper without use of a mask, thereby exposing the second portions of the resist layer within said predetermined area; developing the resist layer; etching away the film underlying all of the exposed portions of the resist layer; removing any remaining portions of the resist layer; and patterning the film in an area corresponding to said predetermined area.
Claim 16
Independent Claim
124 words
A method of making an integrated circuit interconnection comprising the steps of: forming a conductive film on a substrate; applying a layer of positive optical resist over the film; exposing the resist layer by use of a fixed mask, thereby exposing first portions of the resist layer and leaving second portions of the resist layer unexposed; exposing a predetermined area of the resist layer by an optical stepper without use of a mask, thereby exposing the second portions of the resist layer within said predetermined area; developing the resist layer; etching away the film underlying all of the exposed portions of the resist layer; removing any remaining portions of the resist layer; and patterning the film in an area corresponding to said predetermined area.
Claim 17
Dependent Claim
62 words
The method of claim 13, further comprising the steps of: providing a plurality of logic units formed on a surface of the substrate; and testing the logic units to determine which of the logic units are defective; wherein said predetermined area of the resist layer is disposed above a portion of the conductive film associated with interconnection of the defective logic units.
Claim 18
Dependent Claim
26 words
The method of claim 14 wherein the step of patterning the film within said predetermined area forms logic unit interconnections that bypass the defective logic units.
Claim 19
Dependent Claim
22 words
The method of claim 13, wherein the predetermined area is a rectangle of a size less than 100 μm by 100 μm.
Claim 20
Dependent Claim
21 words
The method of claim 13, wherein the predetermined area is less than 1% of a total surface area of the substrate.
Claim 21
Independent Claim
125 words
A method of making an integrated circuit interconnection comprising the steps of: forming a dielectric film on a substrate; applying a layer of negative optical resist over the film; exposing the resist layer by use of a fixed mask, thereby exposing first portions of the resist layer and leaving second portions of the resist layer unexposed; exposing a predetermined area of the resist layer by an optical stepper without use of a mask, thereby exposing the second portions of the resist layer within said are determined area; developing the resist layer; etching away the film underlying all of the non-exposed portions of the resist layer; removing any remaining portions of the resist layer; and patterning the film in an area corresponding to said predetermined area.
Claim 22
Independent Claim
125 words
A method of making an integrated circuit interconnection comprising the steps of: forming a dielectric film on a substrate; applying a layer of negative optical resist over the film; exposing the resist layer by use of a fixed mask, thereby exposing first portions of the resist layer and leaving second portions of the resist layer unexposed; exposing a predetermined area of the resist layer by an optical stepper without use of a mask, thereby exposing the second portions of the resist layer within said are determined area; developing the resist layer; etching away the film underlying all of the non-exposed portions of the resist layer; removing any remaining portions of the resist layer; and patterning the film in an area corresponding to said predetermined area.
Claim 23
Dependent Claim
63 words
The method of claim 18, further comprising the steps of: providing a plurality of logic units formed on a surface of the substrate; and testing the logic units to determine which of the logic units are defective; and wherein said predetermined area of the resist layer is disposed above a portion of the conductive film associated with interconnection of the defective logic units.
Claim 24
Dependent Claim
27 words
The method of claim 19 wherein the step of patterning of the film within said predetermined area forms logic unit interconnections that bypass the defective logic units.
Claim 25
Dependent Claim
22 words
The method of claim 18, wherein the predetermined area is a rectangle of a size less than 100 μm by 100 μm.
Claim 26
Dependent Claim
21 words
The method of claim 18, wherein the predetermined area is less than 1% of a total surface area of the substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-18 | 1999-03-20 | 1999-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-18 | 2003-03-20 | 2003-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-18 | 2007-03-20 | 2007-09-19 | $7700.00 | Window Closed / Lapsed |