Patent US5448513A successfully refreshed from Google Patents.
US5448513A
Expired / Lapsed
US
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Capacitorless DRAM device on silicon-on-insulator substrate
Assignee: University of California, San Diego
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Filing: 1993-12-02
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Granted: 1995-09-05
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Expires: 2013-12-02
Abstract
Abstract A DRAM device has a first semiconductor region of one conductivity on the silicon film of a silicon-on-insulator substrate. A second and a third semiconductor region of the opposite conductivity type are formed in the first semiconductor region. A fourth semiconductor region of the same conductivity type as the first semiconductor region is formed within the second semiconductor region with higher doping concentration. An insulating layer is formed on the semiconductor surface. On top of the insulating layer, a gate electrode is formed and is at least partially overlapped with the first, the second, the third, and the fourth semiconductor region. A storage node is formed in the first semiconductor region between the second and the third semiconductor region where the information is stored. The amount of charge stored in the storage node is controlled by a first transistor including the fourth semiconductor region, the second semiconductor region, the storage node, and the gate electrode. The charge stored in the storage node will affect the characteristics of a second transistor including the third semiconductor region, the storage node, the second semiconductor region, and the gate electrode, thereby the information stored in the storage node is detected.
Inventors
- 👤 Chenming Hu
- 👤 Hsing-Jen Wann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 04:41
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/005; H; H10; H10B; H10B12/00; H10B12/20; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/405; H10D; H10D30/00; H10D30/60; H10D30/711; G11C2211/00; G11C2211/401; G11C2211/4016
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
247 words
A capacitorless dynamic memory cell comprising a body including a support substrate, a first dielectric insulating layer on said substrate, and a semiconductor layer on said first dielectric insulating layer, said semiconductor layer having a surface, a storage node in said semiconductor layer abutting said surface, and electrically isolated from said substrate by said first dielectric insulating layer, said storage node having a net dopant concentration of a first conductivity type, a write bit line region abutting said surface and spaced from said storage node, said write bit line region having a net dopant concentration of said first conductivity type, a buried word line region abutting said surface and positioned between and abutting said storage node and said write bit line region, said buried word line region having a net dopant concentration of a second conductivity type, a read bit line region abutting said surface and said storage node opposite from said buried word line region, said read bit line region having a net dopant concentration of said second conductivity type, a second dielectric insulating layer on said surface, and a gate electrode on said second dielectric insulating layer positioned over said storage node and said buried word line region, said gate electrode functioning with said write bit line region, said buried word line region, and said storage node as a write transistor, and said gate electrode functioning with said buried word line region, said storage node, and said read bit line region as a read transistor.
Claim 2
Dependent Claim
247 words
A capacitorless dynamic memory cell comprising a body including a support substrate, a first dielectric insulating layer on said substrate, and a semiconductor layer on said first dielectric insulating layer, said semiconductor layer having a surface, a storage node in said semiconductor layer abutting said surface, and electrically isolated from said substrate by said first dielectric insulating layer, said storage node having a net dopant concentration of a first conductivity type, a write bit line region abutting said surface and spaced from said storage node, said write bit line region having a net dopant concentration of said first conductivity type, a buried word line region abutting said surface and positioned between and abutting said storage node and said write bit line region, said buried word line region having a net dopant concentration of a second conductivity type, a read bit line region abutting said surface and said storage node opposite from said buried word line region, said read bit line region having a net dopant concentration of said second conductivity type, a second dielectric insulating layer on said surface, and a gate electrode on said second dielectric insulating layer positioned over said storage node and said buried word line region, said gate electrode functioning with said write bit line region, said buried word line region, and said storage node as a write transistor, and said gate electrode functioning with said buried word line region, said storage node, and said read bit line region as a read transistor.
Claim 3
Dependent Claim
22 words
The memory cell as defined by claim 1 wherein said first conductivity type is n-type and said second conductivity type is p-type.
Claim 4
Dependent Claim
33 words
The memory cell as defined by claim 2 wherein electrons from said buried word line region flow into said storage node in writing into said cell and increasing conductance of said read transistor.
Claim 5
Dependent Claim
37 words
The memory cell as defined by claim 2 wherein said storage node is charged with a positive voltage from said write bit line region in writing into said cell and increasing threshold voltage of said read transistor.
Claim 6
Dependent Claim
29 words
The memory cell as defined by claim 4 wherein said body comprises a silicon substrate with said first insulating layer comprising silicon oxide and said semiconductor layer comprising silicon.
Claim 7
Dependent Claim
29 words
The memory cell as defined by claim 1 wherein said body comprises a silicon substrate with said first insulating layer comprising silicon oxide and said semiconductor layer comprising silicon.
Claim 8
Dependent Claim
275 words
A dynamic random access memory comprising an array of memory cells arranged in rows and columns, each memory cell comprising a body including a supporting substrate, a first dielectric insulating layer on said substrate, and a semiconductor layer on said first dielectric insulating layer, said semiconductor layer having a surface, a storage node in said semiconductor layer abutting said surface and electrically isolated from said substrate by said first dielectric insulating layer, said storage node having a net dopant concentration of a first conductivity type, a write bit line region abutting said surface and spaced from said storage node, said write bit line region having a net dopant concentration of said first conductivity type, a buried word line region abutting said surface and positioned between and abutting said storage node and said write bit line region, said buried word line region having a net dopant concentration of a second conductivity type, a read bit line region abutting said surface and said storage node opposite from said buried word line region, said read bit line region having a net dopant concentration of said second conductivity type, a second dielectric insulating layer on said surface, and a gate electrode on said second dielectric insulating layer positioned over said storage node and said buried word line region, said gate electrode functioning with said write bit line region, said buried word line region, and said storage node as a write transistor, and said gate electrode functioning with said buried word line region, said storage node, and said read bit line region as a read transistor, wherein said body of each memory cell comprises a portion of a common substrate.
Claim 9
Dependent Claim
275 words
A dynamic random access memory comprising an array of memory cells arranged in rows and columns, each memory cell comprising a body including a supporting substrate, a first dielectric insulating layer on said substrate, and a semiconductor layer on said first dielectric insulating layer, said semiconductor layer having a surface, a storage node in said semiconductor layer abutting said surface and electrically isolated from said substrate by said first dielectric insulating layer, said storage node having a net dopant concentration of a first conductivity type, a write bit line region abutting said surface and spaced from said storage node, said write bit line region having a net dopant concentration of said first conductivity type, a buried word line region abutting said surface and positioned between and abutting said storage node and said write bit line region, said buried word line region having a net dopant concentration of a second conductivity type, a read bit line region abutting said surface and said storage node opposite from said buried word line region, said read bit line region having a net dopant concentration of said second conductivity type, a second dielectric insulating layer on said surface, and a gate electrode on said second dielectric insulating layer positioned over said storage node and said buried word line region, said gate electrode functioning with said write bit line region, said buried word line region, and said storage node as a write transistor, and said gate electrode functioning with said buried word line region, said storage node, and said read bit line region as a read transistor, wherein said body of each memory cell comprises a portion of a common substrate.
Claim 10
Dependent Claim
38 words
The dynamic random access memory as defined by claim 7 and including a conductive word line interconnecting all gate electrodes of cells along a row, and at least one conductive bit line interconnected to cells along a column.
Claim 11
Dependent Claim
43 words
The dynamic random access memory as defined by claim 8 and including switch means for selectively connecting said at least one conductive bit line to all write bit line regions in said column and to all read bit line regions in said column.
Claim 12
Dependent Claim
41 words
The dynamic random access memory as defined by claim 8 and including a write bit line connected to all write bit line regions in said column and a read bit line connected to all read bit line regions in said column.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-04 | 1999-03-06 | 1999-09-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-04 | 2003-03-06 | 2003-09-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-04 | 2007-03-06 | 2007-09-05 | $7700.00 | Window Closed / Lapsed |