US4725875A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory cell with diodes providing radiation hardness
Assignee: Intersil Corp
•
Filing: 1985-10-01
•
Granted: 1988-02-16
•
Expires: 2005-10-01
Abstract
Abstract A memory cell has a pair of cross-coupled inverters, such as a CMOS pair. Diodes are coupled in series with the transistors to reduce the possibility of radiation-induced currents in the transistors causing a change in state of the cell by providing resistance that increases the cell time constant. The transistors and the diodes are formed in the body of a semiconducting material. The diodes require at most only a small additional cell area as compared with a cell that does not have the diodes.
Inventors
- 👤 Fu-Lung Hsueh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 15:28
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/12; H10B10/125; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D86/00; Y; Y10; Y10S; Y10S257/00; Y10S257/903
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
176 words
An integrated inverter circuit comprising a body of semiconductor material having opposing sides, said body including proximate one of said opposing sides: a first region of a first conductivity type; a second region of a second conductivity type disposed adjacent to said first region; a third region of said first conductivity type disposed adjacent to said second region; a fourth region of said second conductivity type disposed adjacent to said third region to form a diode therewith; a fifth region of said first conductivity type electrically coupled to said fourth region; a sixth region of said second conductivity type disposed adjacent to said fifth region to form a diode therewith; a seventh region of said first conductivity type disposed adjacent to said sixth region; and an eighth region of said second conductivity type disposed adjacent to said seventh region; said integrated circuit further comprising; first and second insulating layers overlying said second and seventh regions, respectively; and first and second gates overlying said first and second insulating layers, respectively, proximate said second and seventh regions, respectively.
Claim 2
Dependent Claim
176 words
An integrated inverter circuit comprising a body of semiconductor material having opposing sides, said body including proximate one of said opposing sides: a first region of a first conductivity type; a second region of a second conductivity type disposed adjacent to said first region; a third region of said first conductivity type disposed adjacent to said second region; a fourth region of said second conductivity type disposed adjacent to said third region to form a diode therewith; a fifth region of said first conductivity type electrically coupled to said fourth region; a sixth region of said second conductivity type disposed adjacent to said fifth region to form a diode therewith; a seventh region of said first conductivity type disposed adjacent to said sixth region; and an eighth region of said second conductivity type disposed adjacent to said seventh region; said integrated circuit further comprising; first and second insulating layers overlying said second and seventh regions, respectively; and first and second gates overlying said first and second insulating layers, respectively, proximate said second and seventh regions, respectively.
Claim 3
Dependent Claim
20 words
The integrated circuit of claim 1, wherein said first conductivity type is N, and said second conductivity type is P.
Claim 4
Dependent Claim
20 words
The integrated circuit of claim 1, further comprising an insulating substrate disposed on the remaining opposing side of said body.
Claim 5
Dependent Claim
16 words
The integrated circuit of claim 3, wherein each of said diodes comprises a junction diffusion diode.
Claim 6
Dependent Claim
16 words
The integrated circuit of claim 3, wherein each of said diodes comprises a buried contact diode.
Claim 7
Dependent Claim
11 words
The integrated circuit of claim 3, wherein said substrate comprises sapphire.
Claim 8
Dependent Claim
23 words
The integrated circuit of claim 1, further comprising a conducting substrate disposed on the remaining one of said opposing sides of said body.
Claim 9
Dependent Claim
35 words
The integrated circuit of claim 7, wherein said fourth region is disposed in said third region, said fifth region is disposed in said sixth region, and each of said diodes comprises a junction diffusion diode.
Claim 10
Dependent Claim
16 words
The integrated circuit of claim 7, wherein said fourth and fifth regions comprise doped polycrystalline silicon.
Claim 11
Dependent Claim
13 words
The integrated circuit of claim 7, wherein said substrate comprises doped bulk silicon.
Claim 12
Dependent Claim
52 words
The integrated circuit of claim 10, wherein said body comprises first and second wells of the second and first conductivity types, respectively, extending a distance into said substrate from a surface thereof, said first well including said first, second and third regions, said second well including said sixth, seventh, and eighth regions.
References Cited (Backward Citations)
US3476617A
Cited
US3983620A
Cited
US4199773A
Cited
US4491859A
Cited
JPS5694670A
Cited
US4468852A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-02-15 | 1991-08-17 | 1992-02-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-02-15 | 1995-08-17 | 1996-02-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-02-15 | 1999-08-17 | 2000-02-16 | $7700.00 | Window Closed / Lapsed |