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US5439836A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for producing a silicon technology transistor on a nonconductor

Assignee: Commissariat à l'Énergie Atomique et Aux Énergies Alternatives
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Filing: 1994-07-13
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Granted: 1995-08-08
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Expires: 2014-07-13
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Abstract

Abstract Method for producing a silicon technology transistor on a nonconductor. This method consists in particular of forming a thin film of silicon (6) on a nonconductor (4) and then a mask (8, 10) including one opening (13) at the location provided for the channel (26) of the transistor; of locally oxidizing (14) the unmasked silicon to form an oxidation film; of eliminating the mask; of forming source (18) and drain (20) regions in the silicon by ion implantation with the oxidation film being used to mask this implantation; of eliminating the oxidation film; and of forming a thin gate nonconductor between the source and the drain and then forming the gate.

Inventors

  • 👤 Benoit Giffard

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 09:21
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6757; H10D30/01; H10D30/021; H10D30/031; H10D30/0321; H10D30/0323; H10D30/6704; H10D30/6713; Y; Y10; Y10S; Y10S148/00; Y10S148/15

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 155 words
Method for producing an MIS transistor comprising a channel, a source and a drain on both sides of the channel and a gate on the channel and separated from the source and the drain, said method comprising the following stages: a) forming a thin film of silicon on a nonconductor, b) forming on the thin silicon film a mask including an opening at the location provided for the channel of the transistor, c) forming a local thick oxidation film by oxidizing the unmasked silicon so as to locally thin the silicon and to form a thinned silicon zone in said silicon film, d) removing the mask, e) effecting ion drain and source implantation in the silicon, the oxidation film being used as a self-aligning mask to mask this implantation, f) removing the oxidation film, g) forming a thin gate nonconductor overlapping the source and the drain, and h) forming the gate on the gate nonconductor.
Claim 2
Dependent Claim 155 words
Method for producing an MIS transistor comprising a channel, a source and a drain on both sides of the channel and a gate on the channel and separated from the source and the drain, said method comprising the following stages: a) forming a thin film of silicon on a nonconductor, b) forming on the thin silicon film a mask including an opening at the location provided for the channel of the transistor, c) forming a local thick oxidation film by oxidizing the unmasked silicon so as to locally thin the silicon and to form a thinned silicon zone in said silicon film, d) removing the mask, e) effecting ion drain and source implantation in the silicon, the oxidation film being used as a self-aligning mask to mask this implantation, f) removing the oxidation film, g) forming a thin gate nonconductor overlapping the source and the drain, and h) forming the gate on the gate nonconductor.
Claim 3
Dependent Claim 30 words
Method according to claim 1, wherein the thin silicon film is formed via an ionic implantation of oxygen in a monocrystalline silicon substrate, followed by annealing of the implanted substrate.
Claim 4
Dependent Claim 66 words
Method according to claim 1, further comprising the following stages that are carried out after the removal of the oxidation film and before forming the gate nonconductor: oxidizing the silicon film to form a sacrificial oxidation film; implanting ions of a type with a conductivity opposite or identical to the source and drain through the sacrificial oxidation film; and eliminating the sacrificial oxidation film after implantation.
Claim 5
Dependent Claim 21 words
Method according to claim 1, wherein the thinned silicon under the gate has a thickness of between 1 to 150 nm.
Claim 6
Dependent Claim 15 words
Method according to claim 1, wherein the gate is made of a doped polycrystalline silicon.
Claim 7
Dependent Claim 21 words
Method according to claim 3, wherein the thinned silicon under the gate has a thickness of between 1 to 150 nm.
Claim 8
Dependent Claim 15 words
Method according to claim 6, wherein the gate is made of a doped polycrystalline silicon.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-08-07 1999-02-06 1999-08-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-08-07 2003-02-06 2003-08-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-08-07 2007-02-06 2007-08-08 $7700.00 Window Closed / Lapsed

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