A high speed silicon-on-insulator device and process of fabricating same

Claim 1

A method of fabricating a silicon-on-insulator integrated circuit wafer, said method comprising the steps of: providing an insulating semiconductor substrate comprising a silicon layer disposed on a buried oxide layer; forming an oxide layer on the silicon layer; depositing a nitride layer on the oxide layer; forming an oversized polysilicon mask on the nitride layer and etching the nitride layer to expose the underlying oxide layer; oxidizing the silicon layer to form a field oxide layer that thins the underlying silicon layer; removing the nitride and field oxide layers; forming a relatively thin layer of oxide on the thinned silicon layer; masking a portion of the surface of the wafer and implanting ions of a first conductivity type into the unmasked portion of the silicon layer to form P-well locations, adjusting the doping concentration and profile to minimize edge and back-channel leakages; masking the previously implanted portion of the surface of the wafer and implanting ions of a second conductivity type into the unmasked portion of the silicon layer to form N-well locations, adjusting the doping concentration and profile to minimize edge and back-channel leakages; removing the thin layer of oxide, depositing photoresist to form an active area mask on the surface, and etching the implanted silicon layer to form active areas; forming a gate oxide layer on the active areas; depositing a layer of polysilicon over the surface of the wafer and depositing phosphorous ions into the layer of polysilicon; forming a polysilicon mask over the layer of polysilicon and etching it to form polysilicon gates; forming an N+ photoresist mask above the N-well locations and implanting phosphorous ions into the unmasked portion of the surface; forming an P+ photoresist mask above the P-well locations and implanting boron ions into the unmasked portion of the surface; disposing a phosphoro-borosilicate glass layer over the surface of the wafer and reflowing it at a predetermined temperature for a predetermined time; masking the phosphoro-borosilicate glass layer and etching it to provide contact locations; and depositing an electrically conductive layer on the surface and etching it to provide contact locations that provide electrical connection between the wafer and external devices.

Claim 18

A method of fabricating silicon-on-insulator integrated circuits having improved edge and back-channel leakage characteristics, said method comprising the steps of: providing an insulating semiconductor substrate comprising a silicon layer disposed on a buried oxide layer; forming an active area mask on the silicon layer; oxidizing the masked silicon layer to form a field oxide layer that thins the underlying silicon layer to provide for fully depleted fabricated devices and to provide relatively thick source and drain regions adjacent the thinned silicon layer; removing the mask and oxidization and then forming a thin layer of oxide on the silicon layer that provides for controlled threshold voltage adjustment; masking a portion of the surface of the wafer and implanting ions of a first conductivity type into the unmasked portion of the silicon layer to form P-well locations. and adjusting the doping concentration and profile to minimize edge and back-channel leakages thereof; masking the previously implanted portion of the surface of the wafer and implanting ions of a second conductivity type into the unmasked portion of the silicon layer to form N-well locations, and adjusting the doping concentration and profile to minimize edge and back-channel leakages thereof; removing the thin layer of oxide and masks; and completing the device fabricating process by forming gates, active areas, and depositing electrically conductive material to provide electrical contacts.